Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire One D260_Compal_LA-5651P_NAV50_60_Rev3.0
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A B C D E
1 1
Compal Confidential
2 2
NAV50/ 60 Schematics Document
Intel Pineview Processor with Tigerpoint + DDRII
3
2010-05-11 3
REV: 3.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 1 of 32
A B C D E
A B C D E
Clock Generator
Compal Confidential CK505 page 8
Model Name : NAV50/ 60
File Name : LA-5651P CRT Conn
page 10
1 ZZZ 1
RGB
Memory BUS(DDRII) DDRII-SO-DIMM
PCB
Pineview page 7
DA60000E420
LCD Conn. LVDS FCBGA 559 1.8V DDRII 667
page 9 22x22mm
Thermal Sensor page 4,5,6
EMC1402
page 5
DMI
X2 mode
GEN1
USB USB Port X2
2
PCI-Express Tigerpoint HDA page 20
2
PCBGA360 BlueTooth
page 15
17x17mm SATA
page 11,12,13,14
CMOS CAM
MINI Card x1 To I/O Board To I/O Board page 9
3G WLAN 10/100 Ethernet HDD
AR8132L page 16 3G
page 15 page 20 page 20
page 15
LPC BUS
Transfermer USB Port x1
To I/O Board Conn.
3 3
page 20
Conn. to I/O Board
Aralia Codec
ALC272 page 20
To I/O board
RJ45
Power ON/OFF DC/DC Interface
page 25
Card Reader
I/O Board ENE6252
page 18
3VALW/5VALW
page 26
ENE KBC SPI page 20
DC IN
page 23
KB926
page 17
0.89VP/1.5VP
AMP & INT INT MIC HeadPhone & SD/MMC/MS
BATT IN 0.9VSP/2.5VSP MIC Jack
page 24 page 28 Speaker CONN
Int.KBD SPI ROM
page 19 page 17
CHARGER 1.8V/VCCP Touch Pad I/O Board
page 25
4
page 27 page19 4
CPU_CORE
page 29
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 2 of 32
A B C D E
A B C D E
1 1
Voltage Rails External PCI Devices
Power Plane Description S1 S3 S5 DEVICE IDSEL # REQ/GNT # PIRQ
VIN Adapter power supply (19V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+0.89V Graphic core power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
+5VALW 5V always on power rail ON ON ON*
2
+5VS 5V switched power rail ON OFF OFF 2
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON EC SM Bus1 address EC SM Bus2 address
Device Address Device Address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. Smart Battery 0001 011X b EMC1402 100_1100
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
3 ICH7M SM Bus address 3
BOARD ID Table(Page 17) Device Address
Clock Generator 1101 001Xb
VCC 3.3V (SLG8SP556VTR)
Ra 100K DDR DIMMA 1010 000Xb
ID BRD ID Rb Vab-Min Vab-Typ Vab-Max
0 R01 (EVT) 0 0V 0V 0V
1 R02 (DVT) 8.2K 0.216V 0.250V 0.289V
NAV50
2 R03 (PVT) 18K 0.436V 0.503V 0.538V
3 R10A (MP) 33K 0.712V 0.819V 0.875V
4 R01 (EVT) 56K 1.036V 1.185V 1.264V
5 R02 (DVT) 100K 1.453V 1.650V 1.759V
NAV60
6 R03 (PVT) 200K 1.935V 2.200V 2.341V
7 R10A (MP) NC 2.500V 3.3V 3.3V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2007/8/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS MB A5651
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401793 D
Date: Friday, May 21, 2010 Sheet 3 of 32
A B C D E
5 4 3 2 1
(7) DDR_A_DQS#[0..7]
PINEVIEW_M
PINEVIEW_M (7) DDR_A_D[0..63]
U71A U71B
REV = 1.1
(7) DDR_A_DM[0..7]
REV = 1.1 DDR_A_MA0 DDR_A_DQS0
AH19 DDR_A_MA_0 DDR_A_DQS_0 AD3
DMI_RX0_R (7) DDR_A_DQS[0..7] DDR_A_MA1 DDR_A_DQS#0
F3 DMI_RXP_0 DMI_TXP_0 G2 DMI_TX0 (13) AJ18 DDR_A_MA_1 DDR_A_DQS#_0 AD2
DMI_RX#0_R F2 G1 DMI_TX#0 (13) DDR_A_MA2 AK18 AD4 DDR_A_DM0
DMI_RX1_R DMI_RXN_0 DMI_TXN_0 (7) DDR_A_MA[0..14] DDR_A_MA3 DDR_A_MA_2 DDR_A_DM_0
H4 DMI_RXP_1 DMI_TXP_1 H3 DMI_TX1 (13) AK16 DDR_A_MA_3
DMI_RX#1_R G3 J2 DMI_TX#1 (13) DDR_A_MA4 AJ14 AC4 DDR_A_D0
DMI_RXN_1 DMI_TXN_1 DDR_A_MA5 DDR_A_MA_4 DDR_A_DQ_0 DDR_A_D1
AH14 AC1
DMI
DDR_A_MA6 DDR_A_MA_5 DDR_A_DQ_1 DDR_A_D2
AK14 DDR_A_MA_6 DDR_A_DQ_2 AF4
DDR_A_MA7 AJ12 AG2 DDR_A_D3
DDR_A_MA8 DDR_A_MA_7 DDR_A_DQ_3 DDR_A_D4
AH13 DDR_A_MA_8 DDR_A_DQ_4 AB2
D DDR_A_MA9 DDR_A_D5 D
AK12 DDR_A_MA_9 DDR_A_DQ_5 AB3
(8) CLK_CPU_EXP# N7 L10 DDR_A_MA10 AK20 AE2 DDR_A_D6
EXP_CLKINN EXP_RCOMPO R162 DDR_A_MA11 DDR_A_MA_10 DDR_A_DQ_6 DDR_A_D7
(8) CLK_CPU_EXP N6 EXP_CLKINP EXP_ICOMPI L9 AH12 DDR_A_MA_11 DDR_A_DQ_7 AE3
L8 R203 49.9_0402_1% DDR_A_MA12 AJ11
EXP_RBIAS 750_0402_1% DDR_A_MA13 DDR_A_MA_12 DDR_A_DQS1
R10 EXP_TCLKINN AJ24 DDR_A_MA_13 DDR_A_DQS_1 AB8
R9 N11 DDR_A_MA14 AJ10 AD7 DDR_A_DQS#1
EXP_TCLKINP RSVD_TP T38 DDR_A_MA_14 DDR_A_DQS#_1
N10 P11 AA9 DDR_A_DM1
RSVD RSVD_TP T39 Must be placed within 500 mils from Pineview-M pins DDR_A_DM_1
N9 RSVD DDR_A_WE# AK22 AB6 DDR_A_D8
(7) DDR_A_WE# DDR_A_WE# DDR_A_DQ_8
DDR_A_CAS# AJ22 AB7 DDR_A_D9
(7) DDR_A_CAS# DDR_A_CAS# DDR_A_DQ_9
DDR_A_RAS# AK21 AE5 DDR_A_D10
(7) DDR_A_RAS# DDR_A_RAS# DDR_A_DQ_10
K2 K3 AG5 DDR_A_D11
RSVD RSVD DDR_A_BS0 DDR_A_DQ_11 DDR_A_D12
J1 RSVD RSVD L2 (7) DDR_A_BS0 AJ20 DDR_A_BS_0 DDR_A_DQ_12 AA5
M4 M2 DDR_A_BS1 AH20 AB5 DDR_A_D13
RSVD RSVD (7) DDR_A_BS1 DDR_A_BS_1 DDR_A_DQ_13
L3 N2 DDR_A_BS2 AK11 AB9 DDR_A_D14
RSVD RSVD (7) DDR_A_BS2 DDR_A_BS_2 DDR_A_DQ_14
AD6 DDR_A_D15
DDR_A_DQ_15
1 OF 6 DDR_A_DQS2
PINEVIEW-M_FCBGA8559 DDR_A_DQS_2 AD8
DDR_CS#0 AH22 AD10 DDR_A_DQS#2
(7) DDR_CS#0 DDR_A_CS#_0 DDR_A_DQS#_2
DDR_CS#1 AK25 AE8 DDR_A_DM2
(7) DDR_CS#1 DDR_A_CS#_1 DDR_A_DM_2
JP16 AJ21
XDP_PREQ# CONN@ DDR_A_CS#_2 DDR_A_D16
(5) XDP_PREQ# 1 1 AJ25 DDR_A_CS#_3 DDR_A_DQ_16 AG8
(5) XDP_PRDY# XDP_PRDY# 2 AG7 DDR_A_D17
2 DDR_CKE0 DDR_A_DQ_17 DDR_A_D18
3 3 (7) DDR_CKE0 AH10 DDR_A_CKE_0 DDR_A_DQ_18 AF10
(5) XDP_BPM#3 XDP_BPM#3 4 DDR_CKE1 AH9 AG11 DDR_A_D19
4 (7) DDR_CKE1 DDR_A_CKE_1 DDR_A_DQ_19
(5) XDP_BPM#2 XDP_BPM#2 5 AK10 AF7 DDR_A_D20
5 DDR_A_CKE_2 DDR_A_DQ_20 DDR_A_D21
6 6 AJ8 DDR_A_CKE_3 DDR_A_DQ_21 AF8
C435 DMI_RX0_R XDP_BPM#1 DDR_A_D22
(13) DMI_RX0 1 2 (5) XDP_BPM#1 7 7 DDR_A_DQ_22 AD11
0.1U_0402_10V7K (5) XDP_BPM#0 XDP_BPM#0 8 M_ODT0 AK24 AE10 DDR_A_D23
8 (7) M_ODT0 DDR_A_ODT_0 DDR_A_DQ_23
9 M_ODT1 AH26
C436 9 (7) M_ODT1 DDR_A_ODT_1
1 2 DMI_RX#0_R (5,13) H_PWRGD R354 1 @ 2 1K_0402_5% 10 AH24 AK5 DDR_A_DQS3
(13) DMI_RX#0 10 DDR_A_ODT_2 DDR_A_DQS_3
0.1U_0402_10V7K R347 1 @ 2 1K_0402_5% 11 AK27 AK3 DDR_A_DQS#3
C (13) SLPIOVR# 11 DDR_A_ODT_3 DDR_A_DQS#_3 C
(8) CPU_ITP 12 AJ3 DDR_A_DM3
C437 12 DDR_A_DM_3
(13) DMI_RX1 1 2 DMI_RX1_R (8) CPU_ITP# 13 13 DDR_A_D24
0.1U_0402_10V7K +VCCP 14 14 DDR_A_DQ_24 AH1
PLTRST# 1 R348 2 1K_0402_1% 15 M_CLK_DDR0 AG15 AJ2 DDR_A_D25
C438 DMI_RX#1_R (5,13,15,17,20) PLTRST# 15 (7) M_CLK_DDR0 DDR_A_CK_0 DDR_A_DQ_25
(13) DMI_RX#1 1 2 @ 16 M_CLK_DDR#0 AF15 AK6 DDR_A_D26
16 (7) M_CLK_DDR#0 DDR_A_CK_0# DDR_A_DQ_26
0.1U_0402_10V7K 17 M_CLK_DDR1 AD13 AJ7 DDR_A_D27
17 (7) M_CLK_DDR1 DDR_A_CK_1 DDR_A_DQ_27
(5) XDP_TDO XDP_TDO 18 M_CLK_DDR#1 AC13 AF3 DDR_A_D28
18 (7) M_CLK_DDR#1 DDR_A_CK_1# DDR_A_DQ_28
(5) XDP_TRST# XDP_TRST# 19 AH2 DDR_A_D29
19 DDR_A_DQ_29
Close to CPU (5)
(5)
XDP_TDI
XDP_TMS
XDP_TDI
XDP_TMS
20
21
20
AC15
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