Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire One D270_Quanta_ZE7_RevC3C
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ZE7 Block Diagram (Intel Cedar Trail-M Platform) 01
CLK Gen.
DDI0
Cedarview-M SLG8LV631V P2
HDMI 1.3a 400 / 640MHz
HDMI CONN
A P17 DC(3.5W) & DC(6.5W) A
(32nm)
DDR III,800/1066 MT/s UNBUFFERED
DDI1 Micro-FCBGA8 DDRIII SODIMM
1366x768 (22x22mm) Channel A RC-B/F
CLK2/3, H=4 P4
LVDS 18bit,SC
LVDS/eDP CONN 0ohm 1366x768
P18
DAC
1920x1200
VGA CONN P5~9
P18
B
x2 DMI Gen1 B
PCIE Gen1
0
RTL8105TA-VC-CG
P22 Tigerpoint (NM10)
3 5 1.5W
Mini card2
P25 vFBGA
(360 balls,17x17mm)
RJ45 CONN HD AUDIO I/F Audio CODEC MIC In Jack
P22 1 Mini card1 7 Realtek 271X P20 Analog MIC
2 P25
Speaker Header (2W) P20
RTS5209-GR
MM-SIM CARD 4
CARDREADER
P25
P26
USB interface 6
5 IN1 CARDREADER module
P19 0 SATA II I/F Mobile 2.5" HDD
C C
SD3.0, MS, MS PRO, P24
xD, MMC P26
3
USB PORT
0 1 2
Left P21 USB 2.0
P10~15
USB PORT USB PORT CCD
Right Down P21 Right Up P18
P21
EC Nuvoton NPCE791L
P27
D
BATTERY CHAGER Discharge/+1.8V/
DDR 1.5VSUS Keyboard Touch Pad SPI Flash Charger PWM FAN D
P29 P32 +3.3V_PRIME P34
P19 P19 P27 P29 P6
Thermal Protection
SYSTEM
P30
+1.05V P35
5V/3V PCU P33
CPU Core Quanta Computer Inc.
Gfx Core PROJECT : ZE7
P31 Size Document Number Rev
Block Diagram C3C
Date: Wednesday, August 31, 2011 Sheet 1 of 42
1 2 3 4 5 6 7 8
5 4 3 2 1
CLK GEN (CLK) 02
+3V VDD_CLK_3.3V VDD_CLK_1.5V +1.5V
R219 1 2 2.2/J_6 L27
PBY160808T-301Y-N/2A/300ohm_6
L32
C225 C277 C224 <20100819_FAE Poyueh> Add 2.2ohm resistor for noise suppress
PBY160808T-301Y-N/2A/300ohm_6
D D
.1U/10V_4 .1U/10V_4 10U/10V_8
C285 C278 C254 C242
Place close to L32 Place close to L27
10U/10V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4
0.1uF near every power pin
U12
0.1uF near every power pin
5 VDD_REF_3.3 VDD_CORE_1.5 23
9 VDD_PCI_3.3 VDD_CORE_1.5 45
<20100803_Sam> Reserve 0ohm to connect to CK505, 10Kohm pull up is required.
VDD_IO can be ranging from 1.05V to 3.3V. 14 VDD_48M_3.3
36 PM_STPPCI#_R R251 *0/J_4
+1.05V PCI_STOP# PM_STPPCI# [13]
30 42 PM_STPCPU#_R R229 *0/J_4 PM_STPCPU# [13] From SB
VDD_SRC_IO_1.05 CPU_STOP#
VDD_CLKIO_1.05V 35 53
VDD_SRC_IO_1.05 CPU_0 CLK_MCH_BCLK [6]
CPU_0# 52 CLK_MCH_BCLK# [6] To CPU (Host CLK) 100 MHz
L28 48
2A/300ohm_6 VDD_CPU_IO_1.05
R221 *0/short_6 CPU_1 50 CLK_DDR3_REFCLK [8]
CPU_1# 49 CLK_DDR3_REFCLK# [8] To CPU (DDR3 IO CLK) 100 MHz
1
Place close to L28 C228 C229 C249 C253 2
NC
44
NC SRC_1/CPU_ITP CLK_PCIE_LANP [22]
C 13 NC SRC_1/CPU_ITP# 43 CLK_PCIE_LANN [22] To LAN (LAN) 100 MHz C
10U/10V_8 .1U/10V_4 .1U/10V_4 .1U/10V_4 54 NC
SRC_2 41 CLK_PCIE_MNC_P [25]
CG_XOUT 3 40 To Mini Card 2 (3G/Wimax) 100 MHz <20101109> Place R235/ R241/ R248/ R254 close to U13
XTAL_OUT SRC_2# CLK_PCIE_MNC_N [25]
CG_XIN 4
C238 XTAL_IN
0.1uF near every power pin SRC_3 38 CLK_PCIE_MPC_P [25]
33P/50V_4 CG_XIN 37 To Mini Card 1 (WLAN) 100 MHz
SRC_3# CLK_PCIE_MPC_N [25]
SMBDT1 7 SDA
2
Y2 14.318MHZ [4,13,25] SMBDT1 SMBCK1 8 SCL SRC_4 34 CLK_PCIE_DMIP [5]
[4,13,25] SMBCK1
Load Capacitance=20p SRC_4# 33 CLK_PCIE_DMIN [5] To CPU (DMI CLK) 100 MHz
C236 FSB 15 32 CLK_PCIE_MMC_P [26]
1
33P/50V_4 CG_XOUT USB48_1/FSB SRC_5
SRC_5# 31 CLK_PCIE_MMC_N [26] To Card Reader (MMC) 100 MHz
R312 33/J_4 USB_48M 17
[10] CLKUSB_48 USB48_2
SRC_6 28 CLK_PCIE_ICH [10]
SRC_6# 27 CLK_PCIE_ICH# [10] To SB (DMI CLK) 100 MHz
R293 33/J_4 FSC 6
[13] 14M_ICH REF/FSC
18 DREFCLK_R R299 *0/J_4
Crystal place within 500mil of CK505 DOT96/SRC7 DREFCLK#_R R300 *0/J_4
DREFCLK [5]
DOT96#/SRC7# 19 DREFCLK# [5] To CPU (PLL CLK) 96 MHz
R296 22/J_4 ITP_EN 10
[12] PCLK_ICH PCIF/ITP_EN
R304 22/J_4 20 <20110110> DPL_REFSSCCLK is used to drive internal
+3V [27] LCLK_EC LCD_CLK DREFSSCLK [5]
R291 33/J_4 33M_SEL 11 21 To CPU (DPLSS CLK) 100 MHz registers and logics of the display interface and therefore
[25] PCLK_DEBUG 25MHz/PCI_2/SEL_33MHz LCD_CLK# DREFSSCLK# [5]
26
needs to be present at all times.
SATA CLK_PCIE_SATA [11]
12 VSS_PCI SATA# 25 CLK_PCIE_SATA# [11] To SB (SATA CLK) 100 MHz
R311 16
*20K/J_4 22
VSS_48M <20100819> Add 475ohm resistors to prevent current leakage
B VSS_LCD CLKREQ_LAN#_R R204 475/F_4 Control SRC_1 Register B5b6 for CLKREQ_A#
B
24 VSS_SATA CLKREQ_A# 47 CLKREQ_LAN# [22]
39 46 CLKREQ_MPC#_R R199 475/F_4 0 = SRC1, 1=SRC2
VSS_SRC CLKREQ_B# CLKREQ_MPC# [25]
51 29 CLKREQ_MMC#_R R284 475/F_4 Control SRC_3 Register B5b4 for CLKREQ_B#
VSS_CPU CLKREQ_C# CLKREQ_MMC# [26]
56 0 = SRC3, 1=SRC4
VSS_REF HWPG Control SRC_5 Register B5b3 for CLKREQ_C#
CKPWRGD/PD# 55 HWPG [13,16,27]
R310 57 0 = SRC5, 1=SRC6
Thermal Pad
*100K_4 <20110110> CFG input hardware strapping to allocate PLL assignment. C357
LOW = Both CPU and SRC clock drive from PLL3
SLG8LV631V *0.1U/10V_4
<20110221> Reserve 0.1F cap to solve that PCICLK (EC 33MHz) sometimes
will change to 25MHz after flash BIOS and restart in first time issue.
HIGH = CPU clock drive from PLL1, SRC clock drive from PLL3.
Contains 100k pull-down resistor.
+3V
FSC FSB Frequency
0 0 133MHz PM_STPPCI#_R R250 10K/J_4
0 1 166MHz USB_48M C280 *10P/50V_4
R313 *10K/J_4
1 1 200MHz PM_STPCPU#_R R230 10K/J_4
+3V
1 = Pin 43/44 as CPU_ITP 1 0 100MHz <20100720_Sam> Keep 100MHz as default. ITP_EN C259 *10P/50V_4
A R306 10K/J_4 ITP_EN 0 = Pin 43/44 as SRC_1 A
CLKREQ_MPC#_R R213 10K/J_4
FSB C279 *10P/50V_4
R301 10K/J_4 R289 10K/J_4 R317 *10K/J_4 CLKREQ_MMC#_R R279 10K/J_4
+3V +3V +3V
FSC C245 *10P/50V_4
R295 *10K/J_4 33M_SEL 1 = Pin 11 as 33MHz FSC FSB Quanta Computer Inc.
0= Pin 11 as 25MHz R259 *10K/J_4 R318 10K/J_4 CLKREQ_LAN#_R R212 10K/J_4
33M_SEL C266 *10P/50V_4
PROJECT : ZE7
Size Document Number Rev
C3C
CLOCK GENERATOR
Date: Wednesday, August 31, 2011 Sheet 2 of 42
5 4 3 2 1
5 4 3 2 1
03
D D
C C
B B
A A
Quanta Computer Inc.
PROJECT : ZE7
Size Document Number Rev
C3C
Reserved
Date: Wednesday, August 31, 2011 Sheet 3 of 42
5 4 3 2 1
5 4 3 2 1
DDR_STD(DDR) DIMM0 H=4mm 04
+1.5VSUS
2.48A JDIM1B
JDIM1A M_A_DQ[63:0] [8]
[8] M_A_A[15:0] 75 VDD1 VSS16 44
M_A_A0 98 5 M_A_DQ0 76 48
M_A_A1 A0 DQ0 M_A_DQ1 VDD2 VSS17
97 A1 DQ1 7 81 VDD3 VSS18 49
M_A_A2 96 15 M_A_DQ2 82 54
M_A_A3 A2 DQ2 M_A_DQ3 VDD4 VSS19
95 A3 DQ3 17 87 VDD5 VSS20 55
M_A_A4 92 4 M_A_DQ4 88 60
M_A_A5 A4 DQ4 M_A_DQ5 VDD6 VSS21
91 A5 DQ5 6 93 VDD7 VSS22 61
M_A_A6 90 16 M_A_DQ6 94 65
M_A_A7 A6 DQ6 M_A_DQ7 VDD8 VSS23
D
86 A7 DQ7 18 99 VDD9 VSS24 66 D
Populate rules: populate M_A_A8 89 21 M_A_DQ8 100 71
SODIMM1 first M_A_A9 A8 DQ8 M_A_DQ9 VDD10 VSS25
85 A9 DQ9 23 105 VDD11 VSS26 72
Strictly follow the mapping M_A_A10 107 33 M_A_DQ10 106 127
PC2100 DDR3 SDRAM SO-DIMM
M_A_A11 A10/AP DQ10 M_A_DQ11 VDD12 VSS27
between clock/control signal 84 35 111 128
M_A_A12 A11 DQ11 M_A_DQ12 VDD13 VSS28
groups and SODIMMs, as 83 22 112 133
M_A_A13 A12/BC# DQ12 M_A_DQ13 +3V VDD14 VSS29
well as SMB address. Other 119 24 117 134
M_A_A14 A13 DQ13 M_A_DQ14 VDD15 VSS30
configurations/mappings will 80 A14 DQ14 34 118 VDD16 VSS31 138
not M_A_A15 78 36 M_A_DQ15 123 139
A15 DQ15 M_A_DQ16 VDD17 VSS32
39 124 144
PC2100 DDR3 SDRAM SO-DIMM
be supported by MRC DQ16 VDD18 VSS33
109 41 M_A_DQ17 C179 C178 145
[8] M_A_BS0 BA0 DQ17 VSS34
108 51 M_A_DQ18 199 150
[8] M_A_BS1 BA1 DQ18 VDDSPD VSS35
79 53 M_A_DQ19 .1U/10V_4 .1U/10V_4 151
[8] M_A_BS2 BA2 DQ19 VSS36
114 40 M_A_DQ20 77 155
[8] M_CS#2 S0# DQ20 NC1 VSS37
121 42 M_A_DQ21 122 156
[8] M_CS#3 S1# DQ21 NC2 VSS38
M_A_DQ22
+3V DESIGN NOTE: [8] M_CLK2 101 CK0 DQ22 50 125 NCTEST VSS39 161
103 52 M_A_DQ23 162
[8] M_CLK2# CK0# DQ23 VSS40
ADDRESS-(A2)H [8] M_CLK3 102 57 M_A_DQ24 198 167
CK1 DQ24 M_A_DQ25 EVENT# VSS41
[8] M_CLK3# 104 CK1# DQ25 59 [8] DDR3_DRAMRST# 30 RESET# VSS42 168
73 67 M_A_DQ26 172
[8] M_CKE2 CKE0 DQ26 VSS43
R150 74 69 M_A_DQ27 173
[8] M_CKE3 CKE1 DQ27 VSS44
10K/J_4 115 56 M_A_DQ28 +SMDDR_VREF_DQ0 1 178
[8] M_A_CAS# CAS# DQ28 VREF_DQ VSS45
110 58 M_A_DQ29 +SMDDR_VREF_DIMM 126 179
[8] M_A_RAS# RAS# DQ29 VREF_CA VSS46
113 68 M_A_DQ30 184
[8] M_A_WE# W E# DQ30 VSS47
DIMM1_SA0 197 70 M_A_DQ31 185
DIMM1_SA1 SA0 DQ31 M_A_DQ32 VSS48
201 SA1 DQ32 129 2 VSS1 VSS49 189
SMBCK1 202 131 M_A_DQ33 3 190
[2,13,25] SMBCK1 SCL DQ33 VSS2 VSS50
SMBDT1 200 141 M_A_DQ34 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo