Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Aspire TimeLine 5820TG_Quanta_ZR7B_Rev1A
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5 4 3 2 1
VER : 1A
BOM P/N Description
31ZR7MB0000 ZR7B MB(UMA,BT)W/O CPU
31ZR7MB0010 ZR7B MB(SG,MADS,SAM,BT,3G)W/O CPU
D D
Channel A
64MB/128MB x 8
Channel C
P19, 20
Arrandale Madison-Pro
rPGA 989 Park EXT_HDMI
Dual Channel DDR III P4, 5, 6, 7 PCI-E x16
DDRIII-SODIMM1 ATI-GPU
800/1066 MHZ IMC GFX
DDRIII-SODIMM2 EXT_CRT
P14,15
CRT Con.
TS3DV421 P24
P16, 17, 18, 21, 22, 23
EXT_LVDS
FDI DMI
SN74CBT3257 x3
LVDS/CRT
X'TAL SLG8LV595 DMI(x4)
SWITCH
14.318MHz CLOCK USB-8
LVDS/CCD/MIC
INT_CRT
GENERATOR P3 FDI DMI Con.
INT_LVDS P24 Int. MIC P24
CLK
Display
C C
SATA 0
SATA - HDD
P29 INT_HDMI PS8101
SATA
LS P25 HDMI Con.
SATA - ODD SATA 1
P29 EXT_HDMI P25
PCIE-6
PCI-E x1
USB Port USB-1 MINI CARD
USB Ibex Peak-M USB-13
P34 WLAN
P28
USB-3/9/11 PCH
USB/B Con. P34 P8, 9, 10, 11, 12, 13 PCIE-2
(USB Port x3) SIM Card FFC
MINI CARD
USB-10 Conn
3G
USB-4 P28 P28
Bluetooth Con. X'TAL
32.768KHz
P34
B B
PCIE-1 AR8151
Cardreader AU6437-GBL USB-12 X'TAL 25MHz RJ45
GIGA LAN P26
P32
Cardreader control P27
P32
P8 BATTERY RTC X'TAL
25MHz
Azalia SPI SPI ROM
IHDA
P8
LPC
ISL88731A UP6111AQDD ISL62881HRZ-T
LPC Batery Charger P38 +1.05V P42 +VGFX_AXG P46
Int. MIC ALC271X-GRR NPCE781 X'TAL RT8206B RT8207A TPS54418RTE x2
AUDIO CODEC P30 EC P37 32.768KHz 3V/5V P39 +1.5V_SUS P43 +1.8V/+1V P47
ISL62882 MAX8792ETD+T Discharger
CPU core P40 +VGPU_CORE P44 P47
BOM Option Table MIC JACK Speaker Power SW/B Touch Pad
A A
P31 P31 Board Con. Board Con. UP6111AQDD ISL62872 Thermal Protection
Reference Description
P33 P33 P35 +1.1V_VTT P41 +VGPU_IO P45 P48
IV@ for UMA only SKU
SW@ for Switchable Graphic only SKU
MP@ for Madison & Park different parts
for different VRAM parts HP/SPDIF K/B Con. W25X16VSS1G EM-6781-T3 Fan Driver Quanta Computer Inc.
VRAM@
P31 P35 SPI FLASH P37 HALL SENSOR (PWM Type) P35
3G@ for 3G function P24 PROJECT : ZR7B
do not stuff Size Document Number Rev
* 1A
Block Diagram
Date: Friday, March 05, 2010 Sheet 1 of 50
5 4 3 2 1
1 2 3 4 5 6 7 8
GPU PWR CTRL Option 1 (Default/ VDDR3 before VDDC)
+3.3V VIN VIN +1.5V +1.5V_SUS +1.8V +5V
VDDR3 +3V_D VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 PG_1.5V_EN VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
MOS (AO3413) ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO6402) AO3413
P22 P44 P45 P47 P43 P43 P22 P22
A
+3_D (0.5A) +VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +1.8V_GPU (3A) +5_GPU A
GPU PWR CTRL Option 2 (VDDR3 after VDDR1)
VIN VIN +1.5V +1.5V_SUS +3.3V +1.8V +5V
VDDC PG_GPUIO_EN VDDCI PG_1V_EN +1V (DP PLL PWR) PG_1.5V_EN VDDR1 +1.5V_GPU VDDR3 +3V_D VDDR4 PG_1.5V_EN BJT dGPU_PWROK MOS
dGPU_VRON dGPU_PWR_EN#
ISL6264 ISL62872 G9334ADJ & MOS MOS (AO4710) MOS (AO3413) MOS (AO6402) AO3413
P44 P45 P47 P43 P22 P43 P22 P22
+VGPU_CORE (20A) +VGPU_IO (4.5A) +1V (3A) +1.5V_GPU (10A) +3_D (0.5A) +1.8V_GPU (3A) +5_GPU
Thermal Follow Chart
Power States
CONTROL
POWER PLANE VOLTAGE DESCRIPTION ACTIVE IN
SIGNAL
B VIN +10V~+19V MAIN POWER ALWAYS ALWAYS B
+VCCRTC +3V~+3.3V RTC POWER ALWAYS ALWAYS NTC
Thermal
+3VPCU +3.3V EC POWER ALWAYS ALWAYS
Protection
+5VPCU +5V CHARGE POWER ALWAYS ALWAYS
+15V +15V CHARGE PUMP POWER ALWAYS ALWAYS
+3V_S5 +3.3V LAN/BT/CIR POWER S5_ON S0-S5 CPU 3V/5 V
H_ORICHOT# PM_THRMTRIP# SYS_SHDN#
CORE PWR
CPU WIRE-AND SYS PWR
+5V_S5 +5V USB POWER S5_ON S0-S5 H/W Throttling
+5V +5V HDD/ODD/Codec/TP/CRT/HDMI POWER MAINON S0
+3V +3.3V PCH/GPU/Peripheral component POWER MAINON S0
SML1ALERT#
+1.5VSUS +1.5V CPU/SODIMM CORE POWER SUSON S0-S3
PCH FAN Driver FAN
+0.75V_DDR_VTT +0.75V SODIMM Termination POWER MAINON S0
+VGFX_AXG variation Internal GPU POWER GFX_ON S0
SM-Bus
+1.8V +1.8V CPU/PCH/Braidwood POWER MAINON S0
C C
+1.5V +1.5V MINI CARD/NEW CARD POWER MAINON S0
EC
+1.1V_VTT +1.05V or +1.1V CPU VTT POWER MAINON S0 CPUFAN#
+1.05V +1.05V PCH CORE POWER MAINON S0
+VCC_CORE variation CPU CORE POWER VRON S0
LCDVCC +3.3V LCD POWER LVDS_VDDEN S0
+5V_GPU +5V SWITCHABLE PWM IC POWER dGPU_PWR_EN# Discrete enable
+GPU_CORE +0.9V~+1.1V GPU CORE POWER +3V_D Discrete enable
+GPU_IO +0.9V~+1.1V GPU I/O POWER PG_GPUIO_EN Discrete enable
+1.5V_GPU +1.5V VRAM CORE POWER PG_1.5V_EN Discrete enable
+1.8V_GPU +1.8V GPU_CRE/LVDS/PLL POWER +1.5V_GPU Discrete enable
+1V +1V DP/PEG POWER PG_1V_EN Discrete enable
D D
Quanta Computer Inc.
PROJECT : ZR7B
Size Document Number Rev
1A
PWR Status & GPU PWR CRL & THRM
Date: Friday, March 05, 2010 Sheet 2 of 50
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
150mA(30mil)
+1.5V L53 595@PBY160808T-181Y-N/2A/180ohm_6 +1.5V_CLK 80mA(20mil)
+VDDIO_CLK L49 PBY160808T/2A/180ohm_6+1.05V
C723 C724 C744
C721 C728 C720 C725
.1u/16V_4 .1u/16V_4 .1u/16V_4
R527 .1u/16V_4 .1u/16V_4 10u/Y5V_8 10u/Y5V_8
*585@0_6 U35
Place each 0.1uF cap as close as
1 VDD_DOT possible to each VDD IO pin. Place
17 VDD_SRC VDD_SRC_I/O 15 the 10uF caps on the VDD_IO plane.
24 VDD_CPU VDD_CPU_I/O 18
20mil 5 VDD_27
+3V L54 BLM18AG601SN1D/200mA/600ohm_6 +3V_CLK 29 3
VDD_REF DOT_96 CLK_BUF_DREFCLK <10>
DOT_96# 4 CLK_BUF_DREFCLK# <10>
CLK_SDATA 31
C750 C477 C745 CLK_SCLK SDA R609 SW@33_4
32 SCL 27M 6 TP12 27M_CLK <17>
7 CLK_VGA_27M_SS R506 *SW@33_4 CLK_27M_SS <17>
4.7u/10V_8 .1u/16V_4 .1u/16V_4 27M_SS C742 *SW@10p/50V_4
R508 33_4 CPU_SEL 30 10
<10> CLK_ICH_14M REF_0/CPU_SEL SRC_1/SATA CLK_BUF_PCIE_3GPLL <10>
SRC_1#/SATA# 11 CLK_BUF_PCIE_3GPLL# <10>
C734 33p/50V_4 13
SRC_2 CLK_BUF_DREFSSCLK <10>
C SRC_2# 14 CLK_BUF_DREFSSCLK# <10> C
XTAL_IN 28
Y5 XTAL_IN +3V
14.318MHz XTAL_OUT 27 16 R491 10K_4
XTAL_OUT *CPU_STOP#
C727 33p/50V_4 2 20
VSS_DOT CPU_1 TP9
8 VSS_27 CPU_1# 19 TP8
9 VSS_SATA CPU_0 23 CLK_BUF_BCLK <10>
12 VSS_SRC CPU_0# 22 CLK_BUF_BCLK# <10>
21 VSS_CPU
IDT: AL003197001 (ICS9LVS3197AKLFT) 26 25 CK_PWRGD_R
VSS_REF CKPWRGD/PD#
33
Realtek: AL000890000 (RTM890N-632-GRT) GND
Silego: AL000595000 (SLG8LV595VTR)
SLG8LV595V
+3V
CPU_CLK select SMBus
B
+1.05V
CLK Enable +3V B
R325
R489
2
R509 2.2K_4 1K/F_4
*10K_4
3 1 CLK_SDATA CLK_SDATA <14,15,28>
<10> ICH_SMBDATA
CK_PWRGD_R
CPU_SEL Q18
3
2N7002K Q37
2N7002K
R513 C747
+3V <40> VR_PWRGD_CK505# 2 R488
10K_4 *10p/50V/COG_4 100K/F_4
1
R551
2
2.2K_4
0 1
3 1 CLK_SCLK CLK_SCLK <14,15,28>
<10> ICH_SMBCLK
A CPU_SEL CPU0/1=133MHz CPU0/1=100MHz Q38 A
2N7002K
(default)
Quanta Computer Inc.
PROJECT : ZR7B
Size Document Number Rev
1A
Clock Generator
Date: Friday, March 05, 2010 Sheet 3 of 50
5 4 3 2 1
5 4 3 2 1
AUBURNDALE/CLARKSFIELD PROCESSOR (DMI,PEG,FDI) AUBURNDALE/CLARKSFIELD PROCESSOR (CLK,MISC,JTAG)
Processor Compensation Signals
U33A U33B
B26 R434 49.9/F_4 R462 20/F_4 H_COMP3 AT23
PEG_ICOMPI COMP3 T38
A26 A16 CLK_CPU_BCLK <11>
PEG_ICOMPO BCLK
MISC
MISC
A24 B27 R461 20/F_4 H_COMP2 AT24 B16 T37 CLK_CPU_BCLK# <11>
<8> DMI_TXN0 DMI_RX#[0] PEG_RCOMPO COMP2 BCLK#
C23 A25 R435 750/F_4
<8> DMI_TXN1 DMI_RX#[1] PEG_RBIAS R128 49.9/F_4 H_COMP1 T44
CLOCKS
<8> DMI_TXN2 B22 PEG_RXN[0..15] <16> G16 AR30
DMI_RX#[2] PEG_RXN0 COMP1 BCLK_ITP T48
<8> DMI_TXN3 A21 K35 AT30
D DMI_RX#[3] PEG_RX#[0] PEG_RXN1 R459 49.9/F_4 H_COMP0 BCLK_ITP# D
J34 AT26
PEG_RX#[1] PEG_RXN2 COMP0
<8> DMI_TXP0 B24 J33 E16 CLK_PCIE_3GPLL <10>
DMI_RX[0] PEG_RX#[2] PEG_RXN3 PEG_CLK
<8> DMI_TXP1 D23 G35 D16 CLK_PCIE_3GPLL# <10>
DMI_RX[1] PEG_RX#[3] PEG_CLK#
DMI
DMI
B23 G32 PEG_RXN4 T52 AH24
<8> DMI_TXP2 DMI_RX[2] PEG_RX#[4] SKTOCC#
A22 F34 PEG_RXN5 A18 DPLL_REF_SSCLK <10>
<8> DMI_TXP3 DMI_RX[3] PEG_RX#[5] DPLL_REF_SSCLK
F31 PEG_RXN6 A17 DPLL_REF_SSCLK# <10>
PEG_RX#[6] PEG_RXN7 H_CATERR# DPLL_REF_SSCLK#
D24 D35 AK14
<8> DMI_RXN0 DMI_TX#[0] PEG_RX#[7] Use reverse type CATERR#
THERMAL
THERMAL
G24 E33 PEG_RXN8
<8> DMI_RXN1 DMI_TX#[1] PEG_RX#[8]
F23 C33 PEG_RXN9 Layout Note: Place
<8>
<8>
DMI_RXN2
DMI_RXN3 H23
DMI_TX#[2]
DMI_TX#[3]
PEG_RX#[9]
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