Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Extenza 5210_5610 TravelMate 5310_5710_Wistron_Dallen_Rev-1
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A B C D E
SYSTEM DC/DC
MAX8744 37
Project code: 91.4V401.001 INPUTS OUTPUTS
PCB P/N : 48.4T307.0SA
3D3V_S5(6A)
Revision : 06259 -1
Mobile CPU
DCBATOUT 5V_S5 (6A)
5V_AUX_S5
4 CLK GEN. Yonah 478 G792 4
RTM865T-433 74.00792.A79
19 SYSTEM DC/DC
71.00865.B0W 3 Celeron M PCB STACKUP
Max8717 38
62.10079.001 4, 5 TV Out
14 TOP INPUTS OUTPUTS
VCC 1D05V_S0(12A)
HOST BUS 400/533/[email protected] CRT DCBATOUT
14 1D8V_S3(8.5A)
DDR2 DVI S
533/667 MHz 43
533/667 MHz Calistoga
AGTL+ CPU I/F
LCD S
TPS51100
DDR_VREF_S0
39
14 GND 1D8V_S3
11,12 DDR Memory I/F
(1.5A)
DDR_VREF_S3
INTEGRATED GRAHPICS BOTTOM
DDR2 533/667 MHz LVDS, CRT I/F MXM conn. APL531230 39
533/667 MHz 71.CALIS.00U
27
6,7,8,9,10 3D3V_S0 2D5V_S0(130 mA)
11,12 X4 DMI
3 C-Link0 3
400MHz APL5912 39
Line In PCMCIA I/F PCMCIA
1D8V_S3 1D5V_S0(5A)
ALC268 PWR SW SLOT
AZALIA Support
71.00268.00G ICH7M TI CP2211F
25 TypeII
26
29 4 PCIe ports
PCI7412
MIC In PCI/PCI BRIDGE PCI BUS Cardbus
29 ACPI 2.0 Cardreader 1394 MS/MS Pro/xD/ ISL CHARGER
ISL6255 41
2 SATA conn.26 MMC/SD
1 PATA 66/100 5 in 1 INPUTS OUTPUTS
OP AMP 24,25 26
30
G1431 30 8 USB 2.0/1.1 ports
CHG_PWR
ETHERNET (10/100/1000MbE)
INT.SPKR 18V 4.0A
High Definition Audio LAN
GIGA TXFM RJ45 DCBATOUT
UP+5V
OP AMP LPC I/F 23 23
2 BCM5787M 22 5V 100mA 2
G1412 30 Serial Peripheral I/F
Line Out CPU DC/DC
PCIex1 Mini Card MAX8770
(No-SPDIF) Kedron a/b/g/n 35,36
28
INPUTS OUTPUTS
MODEM
MDC Card VCC_CORE_S0
RJ11 21
71.ICH7M.00U
LPC BUS
LPC DCBATOUT
0~1.3V
15,16,17,18 DEBUG 47A
CONN. 33
USB
SATA
PATA
MINI USB KBC SPI I/F
PCI Express Winbond BIOS
New card28
BlueTooth 21 WPC8763L
W25X80-VSS
33
31
Finger Pad 32 Touch INT.
1 P2231NFC1 1
28 HDD 20 ODD 20 Pad 32 KB 32 FIR 31 Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
USB CCD
Title
4 Port21 13 Size Document Number Rev
A3
Dallen -1
Date: Tuesday, February 13, 2007 Sheet 1 of 43
A B C D E
ICH7M Integrated Pull-up
and Pull-down Resistors ICH7-M EDS 17837 1.5V1
Calistoga Strapping Signals and
Configuration EDS 17050 0.71
page 7
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25],
Pin Name Strap Description Configuration
GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#,
ICH7 internal 20K pull-ups CFG[2:0] FSB Frequency Select
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 001 = FSB533
011 = FSB667
4 LDRQ[0], LDRQ[1]/GPIO[41], others = Reserved 4
PWRBTN#, TP[3] CFG[4:3] Reserved
CFG5 DMI x2 Select 0 = DMI x2
DD[7], DDREQ ICH7 internal 11.5K pull-downs 1 = DMI x4 (Default)
CFG6 Reserved
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs CFG7 0 = Reserved
CPU Strap 1 =Mobile CPU(Default)
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16,
Reserved
EE_CS,SPI_ARB, SPI_CLK, SPKR, CFG8
0 = Reverse Lanes,15->0,14->1 ect..
USB[7:0][P,N] ICH7 internal 15K pull-downs CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
Lane Reversal Numbered in order
SATALED# ICH7 internal 15K pull-up
CFG[11:10] Reserved
LAN_CLK ICH7 internal 100K pull-down XOR/ALL Z test 00 = Reserved
CFG[13:12] straps 01 = XOR mode enabled
10 = All Z mode enabled
11 = Normal Operation
(Default)
ICH7M IDE Integrated Series CFG[15:14] Reserved Reserved
3 Termination Resistors CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled (Default) 3
Global R-comp Disable 0 = All R-comp Disable
DD[15:0], DIOW#, DIOR#, DREQ, CFG17 (All R-comps) 1 = Normal Operation (Default)
approximately 33 ohm
DDACK#, IORDY, DA[2:0], DCS1#, CFG18 VCC Select 0 = 1.05V (Default)
1 = 1.5V
DCS3#, IDEIRQ
CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane
Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
ICH7M Functional Strap Definitions page 16 CFG20 SDVO/PCIE
0 = Only SDVO or PCIE x1 is
operational (Default)
Concurrent 1 =SDVO and PCIE x1 are operating
Signal Usage/When Sampled Comment simultaneously via the PEG port
ACZ_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 SDVOCRTL SDVO Present 0 = No SDVO Card present
PCIE Port Config bit1, pulled low.When TP3 not pulled low at rising edge _DATA (Default)
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: History 1= SDVO Card present
offset 224h) NOTE: All strap signals are sampled with respect to the leading
edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC PCIE bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
EE_CS Reserved This signal should not be pull high.
EE_DOUT Reserved This signal should not be pull low.
2 2
GNT2# Reserved This signal should not be pull low.
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GNT5#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit
GPIO17#, Selection. (Config Registers:Offset 3410h:bit 11:10).
GNT4#/ Rising Edge of PWROK. GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
GPIO48
page 17
USB Table
DPRSLPVR Reserved This signal should not be pull high. PCI Routing
GPIO25 Reserved. IDSEL INT REQ GNT
Rising Edge of RSMRST#. This signal should not be pull low.
G:CARDBUS 0 0
INTVRMEN Integrated VccSus1_05 Enables integrated VccSus1_05 VRM when TI7412 AD22 B:1394
VRM Enable/Disable. sampled high F:Flash Media 0 USB1
Always sampled. G:SD Host 1 USB3
LINKALERT# Reserved Requires an external pull-up resistor.
2 USB2
REQ[4:1]# XOR Chain Selection.
1 Rising Edge of PWROK. TBD, Chapter 8. 3 USB4 1
SATALED# Reserved This signal should not be pull low. PCIE Routing 4 FingerPad
Wistron Corporation
SPKR No Reboot. If sampled high, the system is strapped to the LANE1 LAN BCM5787M 5 BlueTooth 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Rising Edge of PWROK. "No Reboot" mode(ICH7 will disable the TCO Timer Taipei Hsien 221, Taiwan, R.O.C.
system reboot feature). The status is readable LANE2 MiniCard WLAN 6 CCD
Title
via the NO REBOOT bit.
LANE3 NewCard WLAN 7 NewCard
TP3 XOR Chain Entrance. This signal should not be pull low unless using Size Document Number Rev
A3
Rising Edge of PWROK. XOR Chain testing.
Dallen -1
Date: Tuesday, February 13, 2007 Sheet 2 of 43
A B C D E
RN42
SRN33J-5-GP-U
DREFSSCLK_1 2 3 DREFSSCLK 7
R177 3D3V_S0 DREFSSCLK#_1
0R0603-PAD R154 3D3V_S0
1 UMA 4 DREFSSCLK# 7
3D3V_48MPWR_S0 1 2 0R0603-PAD
3D3V_CLKGEN_S0 1 2 RN43
1
1
C224 C225 SRN33J-5-GP-U
1
1
1
1
1
1
SC4D7U6D3V3KX-GP
SC1U16V3ZY-GP
DY C219 C206 C217 C204 C221 C202 CLK_MCH_3GPLL_1 2 3 CLK_MCH_3GPLL 7
SC4D7U6D3V3KX-GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
CLK_MCH_3GPLL_1# 1 4 CLK_MCH_3GPLL# 7
2
2
2
2
2
2
2
2
RN44
4 SRN33J-5-GP-U 4
CLK_PCIE_ICH_1 2 3 CLK_PCIE_ICH 16
CLK_PCIE_ICH_1# 1 4 CLK_PCIE_ICH# 16
R201 3D3V_S0
0R0603-PAD
3D3V_CLKPLL_S0 1 2 RN45
SRN33J-5-GP-U
1
1
1
C237 C232 C205 CLK_PCIE_NEW_R 2 3 CLK_PCIE_NEW 28
SC4D7U6D3V3KX-GP
SC1U16V3ZY-GP
SCD1U16V2ZY-2GP
DY CLK_PCIE_NEW#_R 1 4 CLK_PCIE_NEW# 28
2
2
2
RN46
SRN33J-5-GP-U
CLK_PCIE_SATA_1 2 3 CLK_PCIE_SATA 15
CLK_PCIE_SATA_1#1 4 CLK_PCIE_SATA# 15
RN39 SRN33J-5-GP-U
CLK_PCIE_LAN_R 1 4 CLK_PCIE_LAN 22
3D3V_S0 U17 CLK_PCIE_LAN#_R 2 3 CLK_PCIE_LAN# 22
H/L: 100/96MHz RTM865T-433-GP
71.00865.B0W
1
RN38 SRN33J-5-GP-U
R187 31 PCLK_KBC 2 R156 1 22R2J-2-GP PCLKKBC 56 17 DREFSSCLK_1 CLK_PCIE_MINI_1 1 4 CLK_PCIE_MINI1 28
10KR2J-3-GP PCI_2/REQ_SEL SRC_0/DOT96SS DREFSSCLK#_1 CLK_PCIE_MINI_1# 2
3 PCI_3 SRC_0#/DOT96SS# 18 3 CLK_PCIE_MINI1# 28
25 PCLK_PCM 2 R167 1 22R2J-2-GP PCLKPCM 4 PCI_4
5 19 CLK_MCH_3GPLL_1
2
PCI_5 SRC_1 CLK_MCH_3GPLL_1# RN37 SRN33J-5-GP-U
SRC_1# 20
SS_SEL 33 PCLK_FWH 2 R166 1 22R2J-2-GP SS_SEL 9 22 CLK_PCIE_ICH_1 CLK_PCIE_PEG_1 1 4 CLK_PCIE_PEG 27
PCIF_1/DOT96SS_SEL# SRC_2
3
16 CLK_ICHPCI 2 R165 1 22R2J-2-GP PCLKICH 8 PCIF_0/ITP_EN SRC_2# 23 CLK_PCIE_ICH_1# CLK_PCIE_PEG_1# 2 MXM 3 CLK_PCIE_PEG# 27
3
24 CLK_PCIE_NEW_R
SRC_3
1
16 PM_STPPCI# 55 25 CLK_PCIE_NEW#_R
R182 PCI_STOP# SRC_3# CLK_PCIE_SATA_1
SRC_4_SATA 26
DY 10KR2J-3-GP SRC_4_SATA# 27 CLK_PCIE_SATA_1#
CLK_PCIE_LAN_R
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