Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer Ferrari 1100_Wistron_Ferrari7_RevSA
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5 4 3 2 1
PAGE3;RESERVE RN65~71 P/L 49.9ohms for ICS951464
PAGE3;CHANGE R107,R108 from 47.5 ohms TO 0ohm;Need CHECK!!
PAGE14;CHANGE LCD1;PIN27 TO TP105;RESERVE FOR LIGHT_SENSOR
PAGE14;CHANGE LCD1;PIN24 TO 5V POWER RAIL FOR LED DRIVER BOARD IC ENABLE PIN(HIGH ACTIVE)
PAGE14;CHANGE F1 TO 4A
PAGE14;P/U TMDS_DDC_DAT TO 3D3V_S0,ADD R471
PAGE15;CHANGE R184,R185,R188 FROM 75ohms TO 150 ohms
D PAGE19;SWAP USB PAIR OF FT AND MINICARD D
PAGE27;CHANGE Q11 TO 84.00143.B1K
PAGE30;CHANGE C389,C390 TO 1uF,X5R
PAGE30;CHANGE R450,R453 TO 14Kohms
PAGE30;CHANGE R459,R463 TO 40.2ohms
PAGE30;CHANGE R458,R462 TO 33ohms
PAGE31;ADD R472 AND P/H TO 3D3V_S0 FOR CAPA_INT#
PAGE31;CHANGE R347 TO 4.7Kohms(E51_TxD P/L)
PAGE31
1.KBC Beep change from A_PWM0(32) to GPIO56(31)
2.Power LED change from GPIO32(65) to A_PWM0(32)
3.e-Button LED change from GPIO43(20) to A_PWM1(118)
C C
B B
LAYOUT
Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
A A
Hsichih, Taipei
Title
Change List
Size Document Number Rev
A
Ferrari 7 SA
Date: Thursday, August 02, 2007 Sheet 1 of 47
5 4 3 2 1
5 4 3 2 1
Ferrari 7 Block Diagram
PCB Layer Stackup
Friday Practice (SA) L1: Component
Ver:Saturday Practice (SB)
Qualifying(SC) L2: GND
Race(-1) L3: Signal
DDR2 SODIMM L4: VCC
2006/04/17
D DIMM1
DDR II 533/667/800
AMD L5: Signal
L6: Signal
D
DDR2 SODIMM K8 Rev.G Project code: ezDockII/II+ L7: GND
DDR II 533/667/800
DIMM2 S1g1 Socket PCB P/N : L8: Component
USB/Express
REVISION : Card/MediaBay/1394*2port CPU V_CORE
Power Switch HyperTransport
OUT
16x16 ISL6264 38/39
IN
P2231NFC1
RJ45/RJ11/PS2*2/Serial INPUT OUTPUT
New card PCI-E x 1 Port/Parallel DCBATOUT VCC_CORE_S0
SidePort DDR2 128MB Port/CRT/TV/DVI-D/SPDIF/MIC
Mini Card PCI-E x 1 64MB x16 in/Line in/Line out/AC Jack SYSTEM DC/DC
802.11a/b/g/n
AMD INPUT
TPS51124
OUTPUT
47
DCBATOUT 1D2V_S0
C C
RJ45 XFORM LAN S-Vedio
CLK GEN.
1D8V_S3
Broadcom
5787MKMLG
PCI-E x 1
RS690T CRT
ICS 9LPRS502
(RTM875T-605)
14.318MHz
SYSTEM DC/DC
ISL6236 46
INPUT OUTPUT
25MHz
LVDS DCBATOUT 5V_S5
12.1" LCD 3D3V_S5
INT. MIC Array
G792 A-Link PCI-E x 4
SYSTEM LDO
TPS51100 48
Line In INPUT OUTPUT
MS/MS Pro/xD/
USB RTL5158
Codec AZALIA MMC/SD 5 in 1 1D8V_S3 0D9V_S3
ALC268
SYSTEM LDO
B
MIC In AMD PCI BUS
TI 1394 INPUT
APL5915
OUTPUT
48
B
AMP 24.576MHz
TSB43AB23PDT CONN 3D3V_S5
3D3V_S0
1D2V_S5
2D5V_S0
G1431 SB600 25MHz
32.768KHz
32.768KHz
3D3V_S0
SYSTEM LDO
1D5V_S0
INT.SPKR ISL6236 46
AZALIA
INPUT OUTPUT
AMP LPC BUS
KBC DCBATOUT
5V_AUX_S5
Winbond SPI 3D3V_AUX_S5
G1412 WPC8768
Line Out
USB Battery Charger
(No-SPDIF)
MODEM USB ISL6255 42
16/17/18/19/20 SIO Touch INT. BIOS INPUTS OUTPUTS
RJ11 MDC Card Pad KB W25X80-VSS
AD+ DCBATOUT
USB x 3
BAT+
SATA CCD 0.3M FIR
USB
A A
LAYOUT
USB
HDD Wistron Incorporated
21F, 88, Hsin Tai Wu Rd
Hsichih, Taipei
PATA USB MINI USB Finger print
Title
Interactive Circuit Map
CDROM
3 Port BlueTooth Size Document Number Rev
A3
Ferrari 7 SA
Date: Thursday, August 02, 2007 Sheet 2 of 47
5 4 3 2 1
5 4 3 2 1
3D3V_S0 R105 3D3V_CLK_VDD
0R3-0-U-GP
1 2
1
1
1
1
1
C259
C617 C618 C621 C616 C285 C287
2
2
2
2
2
SC10U10V5ZY-1GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP
SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SC2D2U10V3ZY-1GP
D D
3D3V_S0
R130
3D3V_CLK_VDD
ICS9LPR464GLFT-GP
SC
1 2 3D3V_48MPWR_S0
SC4D7U6D3V3KX-GP
1- PLACE ALL SERIAL TERMINATION
1
1
RESISTORS CLOSE TO U800 C286 C288
2D2R3J-2-GP
DY 36 VDDSRC GNDSRC 37
SB 26 27
2
2
SC1U16V3ZY-GP VDDSRC GNDSRC
23 VDDSRC GNDSRC 22
2- PUT DECOUPLING CAPS CLOSE TO U800 14 VDDSRC GNDSRC 15
POWER PIN R486
R127 3000mA.80ohm 46 45 1 2
3D3V_S0 0R3-0-U-GP VDDCPU GNDCPU 475R2F-L1-GP
33 VDDATIG GNDATIG 32
1 2 2 VDDREF GNDREF 1 R129
R350 52 50 3D3V_S0
3D3V_S0 0R3-0-U-GP 3D3V_CLK_VDDA VDDHTT GNDHTT
5 VDD48 GND48 8 2 1
1 2 42 41 10KR2J-3-GP
C289 VDDA GNDA
1
1
SCD01U16V2KX-3GP
3D3V_CLK_VDD SC2D2U10V3ZY-1GP
SCD1U16V2ZY-2GP
C257 C262 40 CLK_IREF
R106 NC#40
2
2
1 2 GAP-CLOSE-PWR-2U 11 DY 1 R359 2
RESET_IN#
1
12 HTREF_CLK 33R2F-3-GP GAP-CLOSE-PWR-2U 53 10KR2J-3-GP TP79
PD
5
6
7
8
R103 1 G96 2 CLK_REQA#
49D9R2F-GP
9,20 SMBD0_SB 10 SMBDAT 1
C RN29 TPAD28 C
SRN10KJ-6-GP 9,20 SMBC0_SB 1 G97 2 9 SMBCLK CLKREQC# 29 2 3 SRN33J-5-GP-U CLK_PCIE_DOCK 28
28 1 RN32 4 CLK_PCIE_DOCK# 28
2
HTREF_CLK_R CLKREQB#
51 HTTCLK0 CLKREQA# 49
2 3 SRN33J-5-GP-U CLK_PCIE_MINI1 29
4
3
2
1
CLK_PCIE_DOCK_R 1 RN33 4 CLK_PCIE_MINI1# 29
54 12 CLK_PCIE_DOCK#_R
FS2/REF2 SRCCLKT5 CLK_PCIE_MINI_R
55 FS1/REF1 SRCCLKC5 13 2 3 SRN33J-5-GP-U SBSRC_CLK 17
56 CLK_PCIE_MINI#_R 1 RN34 4 SBSRC_CLK# 17
FS0/REF0 SBSRC_CLK_R
SRCCLKT4 16
33R2F-3-GP 1 2 R352 FS2 17 SBSRC_CLK#_R
12 NB_OSC 22R2F-1-GP R355 FS1 SRCCLKC4 CLK_PCIE_NEW_R
20 SB_OSC_CLK 1 2 44 CPUCLK8T1 2 3 SRN33J-5-GP-U CLK_PCIE_NEW 29
33R2F-3-GP 2 R3561 FS0 43 18 CLK_PCIE_NEW#_R 1 RN35 4
28 CLK14_SIO CPUCLK8C1 SRCCLKT3 CLK_PCIE_NEW# 29
SRCCLKC3 19
261R2F-GP R104 SBLINK_CLK_R SRN33J-5-GP-U
SB 48 CPUCLK8T0 1
RN30
4 SBLINK_CLK 12
47 20 SBLINK_CLK#_R 2 3 SBLINK_CLK# 12
47D5R2F-1-GP R107 CPUCLK_R CPUCLK8C0 SRCCLKT2
6 CPUCLK 2 1 SRCCLKC2 21
47D5R2F-1-GP 2 1 R108 CPUCLK#_R CLK_PCIE_LAN_R 1 4 SRN33J-5-GP-U CLK_PCIE_LAN 24
6 CPUCLK#
31 24 CLK_PCIE_LAN#_R 2 RN27 3 CLK_PCIE_LAN# 24
SRN33J-5-GP-U 4 ATIGCLKT1 SRCCLKT1
12 NBSRC_CLK 1 30 ATIGCLKC1 SRCCLKC1 25
3 RN28 2 SC33P50V2JN-3GP 2 1 C270
12 NBSRC_CLK#
NBSRC_CLK_R 35 39
ATIGCLKT0 SRCCLKT0
1
2
NBSRC_CLK#_R 34 38
ATIGCLKC0 SRCCLKC0 R115 X2
R358 1MR2J-L2-GP
DY
X-14D31818M-35GP
20 CLK48_USB 2 33R2F-3-GP
1 CLK48_USB_R 6 4 C278
1
48MHZ_0 X2
7 3 2 1
2
TPAD30 TP31 48MHZ_1 X1
B U35 SC27P50V2JN-2-GP B
71.95146.C0W
HOSONIC
CLK48_USB
1
RN65 SRN49D9F-GP EC82
CLK_PCIE_NEW#
SCD1U16V2ZY-2GP
1 4 DY
2
CLK_PCIE_NEW 2 3
RN66
SBLINK_CLK# 2 3 SRN49D9F-GP
SBLINK_CLK 1 4
Check SLGO EXT CLK XSL84606 (56 Pin) or XSL84605 (64 Pin) pin to pin compatable with ICS951464 RN67 SRN49D9F-GP
SBSRC_CLK# 1 4
SBSRC_CLK 2 3
RN68
NBSRC_CLK# 2 3 SRN49D9F-GP
NBSRC_CLK
EXT CLK FREQUENCY SELECT TABLE(MHZ) 1 4
RN69 SRN49D9F-GP
FS2 FS1 FS0 CPU SRCCLK HTT PCI USB COMMENT CLK_PCIE_MINI1# 1 4
[2:1] CLK_PCIE_MINI1 2 3
RN70
LAYOUT
A 0 0 0 Hi-Z 100.00 Hi-Z Hi-Z 48.00 Reserved CLK_PCIE_LAN# 2 3 A
CLK_PCIE_LAN 1 4
0 0 1 X 100.00 X/3 X/6 48.00 Reserved
RN71 SRN49D9F-GP Wistron Corporation
0 1 0 180.00 100.00 60.00 30.00 48.00 Reserved CLK_PCIE_DOCK# 2 3 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
CLK_PCIE_DOCK 1 4 Taipei Hsien 221, Taiwan, R.O.C.
SB
0 1 1 220.00 100.00 36.56 73.12 48.00 Reserved SRN49D9F-GP Title
1 0 0 100.00 100.00 66.66 33.33 48.00 Reserved CLKGEN_ICS951464
1 0 1 133.33 100.00 66.66 33.33 48.00 Reserved Size Document Number Rev
A3 SB
1 1 1 200.00 100.00 66.66 33.33 48.00 Normal ATHLON64 operation
Ferrari 7
Date: Thursday, August 02, 2007 Sheet 3 of 47
5 4 3 2 1
5 4 3 2 1
D D
U53A
NB0HTTCLKOUT1 J5 Y4 CPUHTTCLKOUT1 CPUHTTCLKOUT1 10
10 NB0HTTCLKOUT1 NB0HTTCLKOUTJ1 L0_CLKIN_H1 L0_CLKOUT_H1 CPUHTTCLKOUTJ1
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