Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer TravelMate 6252_6292_Quanta_ZU1_Rev1A
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>> Download Acer TravelMate 6252_6292_Quanta_ZU1_Rev1A documenatation <<
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5 4 3 2 1
ZU1 SYSTEM BLOCK DIAGRAM
P C I DEVICE IDSEL# R EQ# / GNT# Interrupts CLOCK
DVI / 7307 CLOCK GENERATOR
Chrontel Merom 479 CPU
CB1410 AD17 R EQ0# / GNT0# INT A# C K 505/PCI1
CK505
(only for ezDock) uFCPGA Thermal Sensor
MR510 AD18 R EQ1# / GNT1# INTB# C K 505/PCI0
D D
Page 21 T IAB23 AD25 R EQ2# / GNT2# INTE# C K 505/PCI2
Page 2 Page 3
Page 3,4
S-VIDEO CONN FSB
Page 20
667/800 Mhz
DDRII
SDVO Dual Channel DDR2 SO-DIMM 0
LCD CONN TV 533/667 MHz
SO-DIMM 1 RJ45
(12.1"WXGA) LVDS NB Page 18
Page 20 VGA Page 12,13
Crestline
(GM965) Transformer
CRT Port Page 5~11 Page 18
Page 19
X4 DMI interface
Mini Card / Giga Lan
HDD (SATA) SATA
C
WLAN (BCM 5787)
C
Page 26
SB Page 27 Page 18
PATA PCIE-0 PCIE-1
ODD (PATA) PCI-Express
Page 26
USB 2.0 ICH8M
Azalia
Page 14~17
PCI Bus
USB Port x 3
USB0~2 Page 27
LPC
Bluetooth PCMCIA Card Reader
USB4 Page 27 1394
Controller Controller Controller
Super I/O
Finger Printer uR PC8763L (CB 1410) (MR510)
(TI 43AB23)
USB6 Page 29 NS PC87383
Page 28 Page 30 Page 22 Page 23 Page 25
B B
CCD
USB8 Page 20
SPI ROM Touch Pad K/B CONN FIR PCMCIA Card Reader 1394 CONN
Page 28 Page 29 Page 29 Page 30 Page 24 Page 24 Page 25
HP HP AMP
Page 32 Page 31
Audio Codec 5V/3V (ISL6236) 1.25V 1.5V 1.25V
PCI-Express PCIE-2
(ALC268) ezDockII/II+ Page 34 Page 38
INT SPK SPK AMP DVI
Page 32 Page 32 Connector USB3
USB VCORE(ISL6262A) Discharge
PCIE , Lan ,1394
Ser & Par Port 1394*2 Page 35 Page 38
Line in & MIC
Page 32 Page 31 PS2 , VGA, DVI TV out / CRT Switch
SPDIF,SM BUS Page 20 A1A
A
VTT 1.05V (SC411) Charger (ISL6251) (11/2):(1) Re-name. A
MediaBay
(2) Gerber out
Express Card Audio Page 36 Page 39
MDC 1.5 10/100/1G Switch 1.8V (TPS51116)
Page 31 Page 33 Page 18 PROJECT : ZU1
Page 37 Quanta Computer Inc.
Size D ocum ent Num ber R ev
Bloc k Diagram 1A
D ate: T h u r s day, Novem ber 02, 2006 Sheet 1 of 39
5 4 3 2 1
5 4 3 2 1
Clock Generator
Clock Gen I2C
L55
+3V C 288 . 1 U_4
BKP1608HS181-T_6
A1A:(9/24) C 542 0_6 C 294 . 1 U_4 +3V
ICS FAE suggest to change R 436
C2,C4 from 4.7uF to 10uF 1 0U_8 C 287 1 0U_8
ICS9LPRS365BGLFT Q21
R HU0 0 2N06 R 197
SLG8SP512T: AL8SP512K05
2
C 540 . 1 U_4 U1 9 IC(64P)SLG8SP512TTR(TSSOP) 10K_4
VD D _ C K_VDD_PCI 2 48 A1A:(9/20) remove IO_VOUT 3 1 C GDAT_SMB
VDD_PCI IO_VOUT 1 3,16,18,27,33 PDAT_SMB
C 292 . 1 U_4 VD D _CK_VDD_48 9
A1A:(9/28) VD D _ CK_VDD_SRC 16 VDD_48 64 C GCLK_SMB
D Reverse RC0603 footprint for EMI VD D _ CK_VDD_REF VDD_PLL3 SCLK C GDAT_SMB D
61 63
VDD_REF SDA +3V
0_6 C 319 . 1 U_4 VD D _ CK_VDD_SRC 39
CK505 38
VDD_SRC SRC5/PCI_STOP# PM_STPPCI# 16
R 199 VD D _ C K_VDD_CPU 55 37 P M_STPCPU# 16 Q20
VDD_CPU SRC5#/CPU_STOP# R HU0 0 2N06 R 195
2
12 54 C L K_CPU_BCLK_R RP36 1 2 0X2
+ 1.05V_VDD VDD_96_IO CPU0 C LK_CPU_BCLK 3
0_6 C 318 . 1 U_4 20 53 C L K_CPU_BCLK#_R 3 4 10K_4
VDD_PLL3_IO CPU0# C LK_CPU_BCLK# 3
R 444 26 3 1 C GCLK_SMB
VDD_SRC_IO_1 1 3,16,18,27,33 PCLK_SMB
45 51 C L K_MCH_BCLK_R RP35 1 2 0X2
VDD_SRC_IO_3 CPU1 C L K_MCH_BCLK 5
36 50 C L K_MCH_BCLK#_R 3 4
VDD_SRC_IO_2 CPU1# C L K_MCH_BCLK# 5
49
VDD_CPU_IO
47
A1A:(9/20) remove SATACLKREQ function, change R value from 475ohm to 22 ohm SRC8/ITP 46
SRC8#/ITP#
R 188 22_4 P C I_CLK_510_R 1 35 C LK_PCIE_3GPLL#_R RP34 3 4 0X2
23 P C I_CLK_510 PCI0/CR#_A SRC10# CLK_PCIE_3GPLL# 6
34 C LK_PCIE_3GPLL_R 1 2 Pin Active Control signal
SRC10 C LK_PCIE_3GPLL 6
R 434 33_4 P C I_CLK_CB714_R 3
22 P CI_CLK_CB714 PCI1/CR#_B
+3V R 429 10K_4 33 P CIE_CLK_RBS_R R 194 475_4 C L K_MCH_OE# 6
R 433 33_4 PCLK_1394_R SRC11/CR#_H P CIE_CLK_RBS#_R R 185 475_4 32 Low SRC9/9#
25 PCLK_1394 4 32 P CIE_CLKREQ# 33
PCI2/TME SRC11#/CR#_G
R 187 33_4 PCLK_591_R 5 30 C L K _PCIE_EZ1_R RP29 3 4 0X2
28 PCLK_591 PCI3 SRC9 PCIE_CLK1+ 33
+3V R 428 *10K_4 31 C L K _PCIE_EZ1#_R 1 2 33 Low SRC10/10#
SRC9# P CIE_CLK1- 33
R 431 22_4 P C I_CLK_SIO_R 6
2 7,30 P C I_CLK_SIO PCI4/SRC5_EN
R 427 10K_4 44
R 186 22_4 P C L K _ICH_R SRC7/CR#_F
7 43 A1A:(9/24) Base on above table, SWAP SRC3 and SRC9
R 181 *10K_4 PCIF5/ITP_EN SRC7#/CR#_E
+ 3V
C G_ XIN 60 41 C L K _ P CIE_ICH_R RP37 1 2 0X2
15 P C L K _ICH XTAL_IN SRC6 C L K _ PCIE_ICH 15
R 182 10K_4 40 C L K _ P CIE_ICH#_R 3 4
SRC6# C L K _ PCIE_ICH# 15
CG_XOUT 59
XTAL_OUT C L K _ P C IE_MINI1_R RP30 +3V
27 3 4 0X2 C L K _ P CIE_MINI1 27
R 430 33_4 F S A SRC4 C L K _ P C IE_MINI1#_R
10 28 1 2 C L K _ P CIE_MINI1# 27
16 C LKUSB_48 CLK_BSEL0 R 426 2.2K_4 USB_48/FSA SRC4#
C CLK_BSEL1 57 24 C L K _ PCIE_LAN_R RP31 3 4 0X2 C
FSB/TEST/MODE SRC3/CR#_C C L K _PCIE_LAN 18
25 C L K _PCIE_LAN#_R 1 2 R 184 10K_4 P CIE_CLKREQ#
SRC3#/CR#_D C L K _PCIE_LAN# 18
CLK_BSEL2 R 441 10K_4 FSC 62
REF0/FSC/TESTSEL C LK_PCIE_SATA_R RP32
21 3 4 0X2 C LK_PCIE_SATA 14
R 442 22_4 SRC2/SATA C LK_PCIE_SATA#_R
16 1 4 M_ ICH 8 22 1 2 C LK_PCIE_SATA# 14
VSS_PCI SRC2#/SATA#
11 A1A:(9/24) Add PCIE_CLKREQ# PU to +3V
R 443 22_4 VSS_48 D REFSSCLK_R RP41
30 S IO_14M 15 17 1 2 0X2 D REFSSCLK 6
19 VSS_IO SRC1/SE1 18 D REFSSCLK#_R 3 4 D REFSSCLK# 6
A1A:(9/24) FAE : (14M_ICH and SIO_14M) signals trace should be equal length VSS_PLL3 SRC1#/SE2
52
VSS_CPU D R EFCLK_R RP33
23 13 3 4 0X2 D R EFCLK 6
29 VSS_SRC1 SRC0/DOT96 14 D R EFCLK#_R 1 2
VSS_SRC2 SRC0#/DOT96# D REFCLK# 6
A1A:(9/24) ICS FAE suggest R change from 22 to 33 ohm 42
A1A:(9/20) change R value from 33ohm to 22 ohm(Intel check list 1.301) VSS_SRC3
58 56 C K _PW RGD 16
VSS_REF CKPWRGD/PWRDWN#
ICS9LPRS365AGLFT/ SLG8SP512T During initial power-up be used to
sample FSB speed with FSA/B/C
C310 33P_4 C G_ XIN
Clock Gen Differential IO power
( 1 ) P C I2 / T ME: PU be us ed, the CK505 c annot over c loc k any of the c loc k for Trus t Mode s ec urity purpos es .
2
Y2
( 2 )PCI4/SRC5_EN: PU be us ed, the CK505 will be c onfigured to us e Pin37/38 to SRC5 c loc k. + 1 .05V_VDD +1.05V
1 4 . 3 18MHZ If PD be detec t at powe-on,the CK505 will s etting Pin 37/38 to PCI_STOP/CUP_SOTP
(Default is s etting to PCI_STOP/CUP_SOTP)
1
C299 33P_4 CG_XOUT L 26
BKP1608HS181-T_6
( 3 ) P CIF5/ITP_EN: PU be us ed, the CK505 will be c onfigured to us e Pin46/47 to CPU ITP c loc k.
EMI FIL TER BKP1608HS181-T(180,1.5A)
If PD be detec t at powe-on,the CK505 will s etting Pin 46/47 to SRC8 C 320 C 309 C 300 C 301 C 316 C 314 C 317 C 290 C315 C 291 C 293
B XTAL length < 500mils (Default is s etting to SRC8) B
* 10U_8 * 1 0U_8 * 1 0U_8 1 0 U_8 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4 . 1 U_4
R 432 * 33_4 PCLK_1394_R ( 4 )SLG8SP512 Pin 6 s elec t Pin 17, 18 output is LCDCLK or 27 M, PD is LCDCLK, PU is 27 M ,
28 P CLK_DEBUG
Pin 37, 38 will fixed be us e CPU_Stop and PCI_Stop.
BIOS/ ERIC 0 .1U close to each VDD_IO Power pin
(5)SLG505YC64 CK505 Standar parts follow s tandar s etting
IF M/B NEED LPC DEBUG PORT, \THEN STUFF THIS RESITER.
CPU Clock select
BSEL Frequency Select Table
R 180 0_4 CLK_BSEL0
3 C PU_BSEL0 MC H_BSEL0 6
FSC FSB FSA Frequency
+ 1 .05V_CPU R 425 *56_4
0 0 0 266Mhz
R 179 1K_4
A1A: (10/23) stuff
0 0 1 133Mhz
R 440 0_4 CLK_BSEL1 0 1 1 166Mhz
3 C PU_BSEL1 MC H_BSEL1 6
R 439 *0_4 0 1 0 200Mhz
A1A: (9/20) Remove 0ohm
A A
+ 1 .05V_CPU R 198 1K_4 1 1 0 400Mhz
A1A: (10/23) stuff
1 1 1 Reserved
R 448 0_4 CLK_BSEL2
3 C PU_BSEL2 MC H_BSEL2 6
1 0 1 100Mhz PROJECT : ZU1
R 449 *0_4
1 0 0 333Mhz Quanta Computer Inc.
R 447 1K_4 Size D ocum ent Num ber R ev
+ 1 .05V_CPU
CLK. GEN./ CK505 1A
A1A: (10/23) stuff
D ate: T h u r s day, Novem ber 02, 2006 Sheet 2 of 39
5 4 3 2 1
5 4 3 2 1
CPU Thermal monitor
U3 0 A
5 H_ A# [16:3]
H_ A #3 J4 H1
A[3]# ADS# H_ ADS# 5
CPU(HOST)
ADDR GROUP 0
H_ A #4 L5 E2
A[4]# BNR# H_ B NR# 5 + 3V
H_ A #5 L4 G5
A[5]# BPRI# H_ B PRI# 5
H_ A #6 K5
H_ A #7 A[6]#
M3 H5 H_ D EFER# 5
H_ A #8 A[7]# DEFER#
N2 F21 H_ D R D Y# 5
H_ A #9 A[8]# DRDY#
J1 E1 H_ D B SY# 5
H_ A#10 A[9]# DBSY#
N3
H_ A#11 A[10]#
P5 F1 H_BREQ#0 5
H_ A#12 A[11]# BR0# A1A:(9/29) change from MBCLK/MNDATA to 2ND_MBCLK/2ND_MBDATA
P2
A[12]#
CONTROL
H_ A#13 L2 D20 H_ IE RR# R 109 56.2_4 + 1.05V_CPU
H_ A#14 A[13]# IERR# +3V R 388 R 387 R 385
P4 B3 H_ INIT# 14
H_ A#15 A[14]# INIT#
P1
H_ A#16 R1 A[15]# H4 Q31 10K_4 10K_4 200_6
A[16]# LOCK# H_LOCK# 5
2
D M1 R HU0 0 2N06 L M 86VCC D
5 H_ADSTB0# ADSTB[0]#
5 H_ REQ#[4:0] C1 H_ CPURST# 5
H _REQ#0 K3 RESET# F3 C 466
H_ RS#0 5 28 2 ND_MBCLK 3 1
H _REQ#1 REQ[0]# RS[0]#
H2 F4 H_ RS#1 5
H _REQ#2 REQ[1]# RS[1]# . 1 U_4
K2 G3 H_ RS#2 5
H _REQ#3 J3 REQ[2]# RS[2]# G2 +3V
REQ[3]# TRDY# H_ T R DY# 5
H _REQ#4 L1 U2 7
REQ[4]# Q30 H_ T H ERMDA
5 H_ A#[35:17] G6 H_ HIT# 5
HIT#
2
H_ A#17 Y2 E4 R HU0 0 2N06 8 1
A[17]# HITM# H_ HITM# 5 SCLK VCC
H_ A#18 U5
H_ A#19 A[18]# C 461
R3 AD4 28 2 ND _MBDATA 3 1 7 2
A[19]# BPM[0]# SDA DXP
ADDR GROUP 1
H_ A#20 W6 AD3
H_ A#21 U4 A[20]# BPM[1]# AD1 A1A: (9/4) +3V 6 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo