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5 4 3 2 1
THIS DRAWING AND SPECIFICATIONS, HEREIN, ARE THE PROPERTY OF INVENTEC
CORPORATION AND SHALL NOT BE REPODUCED, COPIED, OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION, INVENTEC CORPORATION, 2009 ALL RIGHT RESERVED.
HSF Property:ROHS
D D
C
ACER C
BAP41/BAP51/BAP52/BXP41/SJM52
UMA+Discrete(SW Gfx)
B
MAIN BOARD B
2009.06.30
A A
EE DATE POWER DATE
DRAWER
DESIGN
CHECK TITLE
INVENTEC
RESPONSIBLE
BAP41/BAP51 (Montevina SFF)
SIZE= VER: SIZE CODE DOC.NUMBER REV
Tuesday, June 30, 2009 A02 FILE NAME: XXXX-XXXXXX-XX C A02 D-CS-1310A2292001-ALG A02
DATE CHANGE NO. REV P/N XXXXXXXXXXXX SHEET 1 of 49
5 4 3 2 1
8 7 6 5 4 3 2 1
1. Schematic Page Description :
Montevina Schematic Ver : A02
1. Title 24. Clock Generator
D D
2. Schematic Page DESCR 25. DDR3 SDRAM SO-DIMM0
3. Block Diagram 26. DDR3 SDRAM SO-DIMM1
4. Annotations 27. ICH9M CPU/SATA(1/4)
5. Schematic Modify 28. ICH9M PCI/PCIE/DMI/USB(2/4)
6. Timing Diagram 29. ICH9M GPIO(3/4)
7. Power Block Diagram 30. ICH9M Power/GND(4/4)
8. Adaptor in/Charge 31. LCD/CRT
9. 5VLA/5VA/3VA 32. KBC ITE8502E-L
10. 3VS/5VS/1.5V (DDR3) 33. IO CN
11. 1.05VS/1.5S/1.8V/1.5VA 34. IO CN
12. Power Latch/1.5VS/SCREW HOLE 35. IO CN
13. CPU Core Power 36. Audio Codec
C
14. GPU Core Power 37. EASY PORT CN/ LEVEL SHIFTER C
15. Penryn Processor(1/2) 38. M92-S2(1/5)
16. Penryn Processor(2/2) 39. M92-S2(2/5)
17. CPU Thermal 40. M92-S2(3/5)
18. Cantiga Host(1/6) 41. M92-S2(4/5)
19. Cantiga DMI/Graph(2/6) 42. M92-S2(5/5)
20. Cantiga DDRIII(3/6) 43. DDR3 VRAM
21. Cantiga Power(4/6) 44. HyBrid Switch
22. Cantiga Power(5/6) 45. dGPU Power
23. Cantiga Ground(6/6) 46. dGPU Power
47. dGPU Power
48. HDD Board
49. TPM Board
B B
A A
TITLE
INVENTEC
BAP41/BAP51 (Montevina SFF)
Schematic Page
SIZE CODE DOC.NUMBER REV
Custom A02 D-CS-1310A2292001-ALG A02
CHANGE by Shiun-Chin Chang DATE Tuesday, June 30, 2009 SHEET 2 of 49
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
3. Block Diagram :
PLL
CPU 22mmx22mm
ICS9LPRS365BKLFT
CPU Thermal Penryn - SFF
D
FAN Thermal TSSP 64P D
P.25
EMC1402 Penryn 956Pin
P.18 Palmrest
P.18 P.15, 16 266MHz+/- x2 (CPU, NB)
100MHz+/- x7
FSB 1.05V 48MHz x2 (ICH, SC)
667/800/1066MHz 33MHz x6
LCD LVDS DDR3 1.5V 14MHz x2 (ICH, SIO)
SODIMM0
SODIMM1
P.31 MCH 27mmx25mm 800/1066MHz 27MHz/96MHz+/-x1
CRT RGB RGB FCBGA 1363pin DDR3 1.5V
P.33 800/1066MHz
Cantiga - SFF
DVI-D EASY TMDS PARADE
P.18-23 P.26
P.33
Port PS8101T
P.48 P.25
DMI x4
VRAM DDR3 M92-S2 PCIE-GFX
16mmx16mm MiniCard #1
512Mb FCBGA 631pin ICH PCI-Express x1 2.5GHz-----Port 1
Minicard
C
WLAN C
P.38
Board Port#1 P.31
PCI-Express x1 2.5GHz-----Port 2 MiniCard #1
ICH9M-SFF Minicard 3G
SATA HDD HDD SATA 150 Board Port#1 P.31
FCBGA 569pin
P.31 Board PCI-Express x1 2.5GHz-----Port 3
Audio GbE RJ45
USB0 USB1 USB2 RTL8111CP
SSD HDD Board
SSD SATA 150 P.33
Port Port Port
P.31 P.31 P.33 P.35 Board
HDA 24MHz
USB3
CR Audio HUBX4 EASY
Board Board Port
IN IN Analog In
IntMic Audio Audio
IN P.33
Stereo
P.37 Codec Board
B EHCI#1 B
Support ALC269X-GR
Out Out Analog Out
USB 2.0/1.1 S0~S3 state
SPK Out Audio
P.33
P.37 P.38 Board
LPC 3.3V 33MHz
USB4 USB7 USB6 USB5 FP
WLAN Camera BlueTooth Finger Printer PMU&KBC 80Port TPM
Board ITE8502F
P.33 P.33 P.33 P.33
P.32 P.31 Board
TPM EASY PORT
USB11 P.33
CR Audio DVI-D HUB USBX4 HP-OUT/MIC-IN RJ45 AC JACK
3G KB LINE-IN/SPDIF
Board Board P.34
P.31
SPI
P.28-31 TMDS (Cantiga 19V
Flash
A
Reserve USB Port3 (ICH9M) RTL8111CP A
ROM
USB8 USB9 P.32 Analog Out (ALC269X)
REALTEK
RTS5159 Port
P.33
GP/FP
Board
Glide Pad
P.33 TITLE
INVENTEC
BAP41/BAP51 (Montevina SFF)
Block Diagram
SIZE CODE DOC.NUMBER REV
Custom A02 D-CS-1310A2292001-ALG A02
CHANGE by Shiun-Chin Chang DATE Monday, June 29, 2009 SHEET 3 of 49
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
4. Net name Description : Power Rail
VCC_CORE
Destination
Penryn SFF HFM:
LFM:
Voltage
1.3319V~1.4375V~1.4591V
0.9221V~0.9625V~0.9739V
S0 Current
18A
1.05VS Penryn SFF : AGTL+ termination 1V~1.05V~1.10V 4.5A
Cantiga GS: Core 0.997V~1.05V~1.102V 8.7A
Voltage Rails Cantiga GS: PCIE 0.9975V~1.05V~1.1025V 1.78A
Cantiga GS:Core+IMEL+HSIO 0.9975V~1.05V~1.1025V 2.898A
DCIN Primary DC system power supply Cantiga GS:VCC_GMCH 0.997V~1.05V~1.102V 10.154A
+5VLA 5.0V always on power rail by LATCH or ACIN Cantiga GS:VCCA_SM_CK and NCTF 0.997V~1.05V~1.102V 37.95mA
D
+5VA 5.0V always on power rail by ECPWON Cantiga GS:VCC_DMI 0.997V~1.05V~1.102V 456mA
D
+3VA 3.3V always on power rail by ECPWON Cantiga GS:VCCA_SM 0.997V~1.05V~1.102V 747.5mA
+5VS 5.0V switched power rail by SLP_S3#_3R Cantiga GS:VTT 0.997V~1.05V~1.102V 852mA
+3VS 3.3V switched power rail by SLP_S3#_3R ICH9M:VCC1_05 0.997V~1.05V~1.102V 1.634A
+1.8VS 1.8V switched power rail by SLP_S3#_3R ICH9M:DMI 0.997V~1.05V~1.102V 48mA
ICH9M:CPU_IO 0.997V~1.05V~1.102V 2mA
VCC_CORE Core Voltage for CPU 1.5VS Penryn SFF PLL 1.425V~1.5V~1.575V 130mA
+1.05VS 1.05V power rail for AGTL+ termination/Core for GMCH by SLP_S3#_3R Cantiga GS: QDAC 1.425V~1.5V~1.575V 0.5mA
+1.25VS 1.25V switched power rail by SLP_S3#_3R Cantiga GS: LVDS 1.71V~1.8V~1.89V 60.31mA
+1.5VS 1.5V power rail for CPU PLL/DMI;PCIE;DDRIII DLLs for GMCH/Core;PCIE Cantiga GS: TVDAC 1.425V~1.5V~1.575V 35mA
for ICH9m by SLP_S3#_3R Cantiga GS: Various PLLS analog supply 1.425V~1.5V~1.575V 485mA
Cantiga GS: VCC_SM_CK 1.425V~1.5V~1.575V 149.5mA
+1.5V 1.5V power rail for DDRII by SLP_S5#_3R Cantiga GS: VCC_SM 1.425V~1.5V~1.575V 3.1625A
0.75VDDT_DDRIII 0.75V DDRII Termination Voltage by SLP_S3#_3R ICH9M:PCIE_ICH 1.425V~1.5V~1.575V 646mA
ICH9M:SATA_ICH 1.425V~1.5V~1.575V 1.342A
ICH9M:VCC_GLAN 1.425V~1.5V~1.575V 80mA
Part Naming Conventions Mini Card:
C = Capacitor Express Card: 1.425V~1.5V~1.575V 650mA
CN = Connector 1.5V Cantiga GS: DDRIII System Memory 1.425V~1.5V~1.575V 3.1A(800M) 4.1A(1067M)
C C
D = Diode 0.75VDDT_DDRIII:DDRIII Terminator: 0.7125V~0.75V~0.7875V 1.0A
F = Fuse 3VS Cantiga GS: HV CMOS 3.135V~3.3V~3.465V 105.3mA
L = Inductor Cantiga GS: VCCS_TVDAC 3.135V~3.3V~3.465V 78mA
Q = Transistor ICH9M:VCC3_3 3.135V~3.3V~3.465V 308mA
R = Resistor ICH9M:VCCGLAN3_3 3.135V~3.3V~3.465V 1mA
RP = Resistor Pack Thermal Sensor: 3.0V~3.3V~3.6V 5mA
U = Arbitrary Logic Device Mini Card: UMTS
Y = Crystal and Osc Express Card: 3.135V~3.3V~3.465V 1.3A
CLK Generator: ICS9LPRS365BKLFT 3.135V~3.3V~3.465V 500mA
Mini Card: WirelessLan
Net Name Suffix Bluetooth:
3.0V~3.3V~3.6V
Super I/O: IT8305E
# = Active Low signal Azalia Codec: ALC262
Azalia MDC:
5. Board Stack up Description 1.8VS
3VA
DVI
ICH9M: RTC
3.0V~3.3V~3.6V
2V~3.3V~3.465V
120mA
6uA
ICH9M:VCCSUS3_3 3.135V~3.3V~3.465V 212mA
B
PCB Layers ICH9M:VCCCL3_3 3.135V~3.3V~3.465V 73mA B
Layer 1 Component Side, Microstrip signal Layer ICH9M:VCCLAN3_3 3.135V~3.3V~3.465V 78mA
LCD: 3.0V~3.3V~3.6V 2A
Layer 2 Ground Plane Lan:AR8131 3.0V~3.3V~3.6V 1A
Layer 3 Stripline Layer Azalia MDC:
Flash ROM: BIOS 3.0V~3.3V~3.6V
Layer 4 Power Plane
Layer 5 Stripline Layer 5VS Cardreader: RTS5159 3.0V~3.3V~3.6V
Azalia Codec: ALC269 3.0V~3.3V~3.6V
Layer 6 Stripline Layer HDD: SATA 4.75V~5.0V~5.25V Max: 1.5A ; R/W: 460mA ; STDBY: 70mA
Layer 7 Ground Plane ODD: SATA 4.75V~5.0V~5.25V Max: 1.5A ; R/W: 900mA ; STDBY: 45mA
Audio AMP: G1432
Layer 8 Solder Side,Microstrip signal Layer Inverter:
WebCam 4.75V~5.0V~5.25V 1A
5VA USB: x 2 ports 5VA 2A
USB 5VA 1.5A
Differential Impedance for Microstrip Differential Impedance for Stripline
Host Clock 95 ohm +/- 20% 95 ohm +/- 20% 5VLA Control Power
PCI-E Clock 95 ohm +/- 20% 95 ohm +/- 20%
DDR3 CLK 75 ohm +/- 20% 75 ohm +/- 20% 3VLA EC: ITE8512E 3.0V~3.3V~3.6V 300mA
A DDR3 Strobe 90 ohm +/- 20% 90 ohm +/- 20% A
DMI Bus 95 ohm +/- 20% 95 ohm +/- 20%
PCIE Bus 95 ohm +/- 20% 95 ohm +/- 20%
SDVO 95 ohm +/- 20% 95 ohm +/- 20%
SATA 95 ohm +/- 20% 95 ohm +/- 20%
USB
LVDS
90 ohm +/- 20%
95 ohm +/- 20%
90 ohm +/- 20%
95 ohm +/- 20% TITLE
INVENTEC
Lan 95 ohm +/- 20% 95 ohm +/- 20% BAP41/BAP51 (Montevina SFF)
ANNOTATIONS
SIZE CODE DOC.NUMBER REV
Custom A02 D-CS-1310A2292001-ALG A02
CHANGE by Shiun-Chin Chang DATE Monday, June 29, 2009 SHEET 4 of 49
8 7 6 5 4 3 2 1
5 4 3 2 1
6.Schematic modify Item and History :
D D
C C
B B
A A
TITLE
INVENTEC
BAP41/BAP51 (Montevina SFF)
Schematic Modify
SIZE CODE DOC.NUMBER REV
Custom A02 D-CS-1310A2292001-ALG A02
CHANGE by Shiun-Chin Chang DATE Monday, June 29, 2009 SHEET 5 of 49
5 4 3 2 1
5 4 3 2 1
SYSTEM POWER ON/OFF SEQUENCE Drawing : Wendy, Huang
Power on/off sequence AC insert (without Battery Pack) Power on/off sequence Battery insert Power on/off sequence AC insert(with charge over 95%)
Power on sequence Power off sequence (without AC adapter) Power on sequence Power off sequence
Power on sequence Power off sequence
Always 3.3V Always 3.3V
Always 3.3V
SW OFF: RTCVCC(3.3V) SW OFF: RTCVCC(3.3V)
D SW OFF: RTCVCC(3.3V) High High D
High
5VLA,3VLA 5VLA,3VLA
5VLA,3VLA High High
High
EC_3VLA EC_3VLA
EC_3VLA High
Wake-Up EC For Battery Charge
Low ACIN#(I) ACIN#(I)
ACIN#(I) EC Programming This Pin To High
High
EC Latch EC_AD_ON When Press Power Switch
EC_AD_ON(O) EC_AD_ON(O)
EC_AD_ON(O)
SW ON: PWR_SWIN#(I) SW ON: PWR_SWIN#(I) SW ON: PWR_SWIN#(I)
LATCH_ON(O) LATCH_ON(O) LATCH_ON(O)
3VA,5VA 3VA,5VA 3VA,5VA
RSMRST#(O) RSMRST#(O) RSMRST#(O)
PWR_BTN#(O) PWR_BTN#(O) PWR_BTN#(O)
SUSB#(I) SUSB#(I) SUSB#(I)
SUSC#(I) SUSC#(I) SUSC#(I)
1.5V_DDR 1.5V_DDR 1.5V_DDR
C C
MAIN POWER MAIN POWER MAIN POWER
1.5V_PWRGD(I) 1.5V_PWRGD(I) 1.5V_PWRGD(I)
1.05VS_PWRGD(I) 1.05VS_PWRGD(I) 1.05VS_PWRGD(I)
ALL_SYSPWRGD(O) ALL_SYSPWRGD(O) ALL_SYSPWRGD(O)
VR_ON(O) VR_ON(O) VR_ON(O)
VCORE_GD(I) VCORE_GD(I) VCORE_GD(I)
PM_ICH_PWROK(O) PM_ICH_PWROK(O) PM_ICH_PWROK(O)
Power on/off sequence AC insert(without charge over 95%) Suspend And Resume Sequence (S3) Power on/off sequence after windows shoutdown (WOL enable)
Suspend sequence Resume sequence Suspend sequence Resume sequence
Power on sequence Power off sequence Always 3.3V
Always 3.3V
SW OFF: RTCVCC(3.3V) High
Always 3.3V SW OFF: RTCVCC(3.3V)
High 5VLA,3VLA High
SW OFF: RTCVCC(3.3V)
High 5VLA,3VLA EC_3VLA
High Low
5VLA,3VLA ACIN#(I)
B High EC_3VLA B
Don't Care This Signal EC Keep EC_AD_ON Signal To High When WOL Enable
EC_3VLA EC_AD_ON(O)
ACIN#(I)
System Boot
ACIN#(I) High SW ON: PWR_SWIN#(I)
Full Battery High
System Boot EC Latch This Signal Capacity About EC_AD_ON(O)
95%~100% LATCH_ON(O)
EC_AD_ON(O) EC Keep LATCH_ON Signal To High When WOL Enable
3VA,5VA
SW ON: PWR_SWIN#(I) High
SW ON: PWR_SWIN#(I) High RSMRST#(O)
LATCH_ON(O) PWR_BTN#(O)
LATCH_ON(O) High
3VA,5VA SUSB#(I)
3VA,5VA High
RSMRST#(O) SUSC#(I)
RSMRST#(O)
PWR_BTN#(O) 1.5V_DDR
PWR_BTN#(O)
SUSB#(I) MAIN POWER
SUSB#(I) High
SUSC#(I) 1.5V_PWRGD(I)
SUSC#(I) High
1.5V_DDR 1.05VS_PWRGD(I)
1.5V_DDR
MAIN POWER
MAIN POWER ALL_SYSPWRGD(O)
1.5V_PWRGD(I)
A 1.5V_PWRGD(I) VR_ON(O) A
1.05VS_PWRGD(I)
1.05VS_PWRGD(I) VCORE_GD(I)
ALL_SYSPWRGD(O)
ALL_SYSPWRGD(O) PM_ICH_PWROK(O)
VR_ON(O)
VR_ON(O)
VCORE_GD(I)
VCORE_GD(I)
TITLE
INVENTEC
PM_ICH_PWROK(O) BAP41/BAP51 (Montevina SFF)
PM_ICH_PWROK(O) Time Diagram
SIZE CODE DOC.NUMBER REV
Custom A02 D-CS-1310A2292001-ALG A02
CHANGE by Shiun-Chin Chang DATE Monday, June 29, 2009 SHEET 6 of 49
5 4 3 2 1
8 7 6 5 4 3 2 1
Power Block Diagram :
D D
DCIN 5VA MOS 5VS
TPS51125
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