Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer TravelMate C100_Wistron_TM100_Rev-1
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CPU DC/DC Project Code : 91.48R01.001
Switching Power
MAX1718/MAX1714
TM100 PCB P/N : 01201-1
PCB : 48.48R01.001
INPUTS OUTPUTS CPU
3D3V_S0/2D5V_S0 PCB LAYER
PIII TUALATIN
DCBATOUT VCC_CORE_S0 CLOCK ULV 700MHz~ L1:COMPONENT
VCCT_S0 Genertor
FCBGA L2:GND
PAGE:27,28 ICS9248-61 Page:3 Page:3,4
L3:SIGNAL
HOST BUS L4:SIGNAL
DC/DC&CHARGER 5V_S0
100MHz L5:GND
Switching Power 2D5V_S3/3D3V_S3
CRT
MAX1632/OZT05J02 /2D5VRD_S3 L6:VCC
3D3V_S3 Page:10
SDRAM +3.3V/M+3V/+2.5V/M+2.5V/+5V VGA L7:SIGNAL
INPUTS OUTPUTS 100MHz SMI SM722 L8:SIGNAL
SDRAM*2 33MHz 3D3V_S0
DCBATOUT 3D3V_S5AC LCD L9:GND
Page:8 Page:9
3D3V1_S5AC CORE LOGIC Page:11 L10:COMPONENT
3D3V_S3 Intel 82443MX
3D3V_S0 5V_S0
5V_S0 Page:7 +3.3V/+5V/+12V
12V_S0 IDE BUS SMART Card
HDD Ultra 33 SLOT *1
AD+ BT+ CARDBUS Page:15
Page:13
PAGE:29,30,31 O2 OZ711
/32,33 TARZEN
Page:14 CARDBUS
SLOT *1
OTHER DC/DC Page:15
MAX1792/G913 PCI BUS
INPUTS OUTPUTS XD BUS
3D3V_S0 2D5V_S0 5V_S0 5V_S3 5V_S0 5V_S0
LAN_3D3V_S5AC/ 3D3V_S5AC 3D3V_S0
2D5V_S0 1D5V_S0 SIO KBC DEBUG LAN_2D5V_S5AC/
1D8V_S0 BIOS LAN MINIPCI IEEE 1394
3D3V_S3 2D5V_S3
NS 97338
M38869 ROM PORT RTL8100BL 802.11 TI TSB43AB21
Page:25 Page:23 Page:24 Page:27 Page:17,18 Page:19 Page:16
PAGE:28
AC-LINK
3D3V_S0 5V_S0 5V_S0 5V_S3 5V_S0 3D3V_S0/5V_S0 5VA_S0
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Touch Taipei Hsien 221, Taiwan, R.O.C.
FIR DIGITIZER INTKB USB MODEM AC 97 Title
Pad
IRMS6452 Page:11 Page:23 Page:23 PORT Daughter Codec System Block Diagram
Page:26 0,1 Page:26 Card CS4299-XQ Size Document Number Rev
Page:19 Page:20,21,22 A4
TM100 -1
Date: Thursday, April 04, 2002 Sheet 1 of 35
1. Support S3 State (Suspend To RAM):
* SC -> SD
Page 6:
Wake Up Event Chip Controller
No Description 1.Change Q26 from BSS138 to MMBT3904
Page 7 :
2.GPIO9 : Replace 802.11LED# with OBLAN-80211#
1 PME#_RSM(WOL) LAN Controller RTL8100L Magic Packet/ Wake Up Frame 3.Add smith trigger and debounce RC to solve 100uS drop of SUSB#
Page 10:
2 PWRBTN#_5RSM Banister Wake Event from User 4.Change VGA connecter for ME request
Page 11:
3 LID KBC 5.Change U88-1 control pin from U50-2 to BL2#
6.Replace digitizer reset signal from SUSB# to PCIRST2#
4 Ring IN MDC 7.Add R564 to limit the current
Page 12:
5 Any Key KBC 8.U51-1control signal changed from 3D3V_S0 to PRE_SUSC#
6 BL2# KBC Page 13:
9.Add D34 to prevent park voltage of HDD under -0.3V
Page 14:
10.Add DTC124EKA and dummy R546 to be the gate of PME# of OZ711.
Page 16:
2. Change notice : 11.Change 1394 connecter for ME request
* Before SMT of SA:: Page 17:
1>0R3-0-U ( 63.R0004.151) DEL: R260, R211, R214 ADD: R261, R209, R216, R263 12.Use U90 as the gate to control PCIRST2# to OBLAN and PL 10K to PCIRST2#_LAN
2>Charger firmware U48 from P/N:71.12509.00A(PIC) to P/N:71.00012.00A(ATMEL) 13.Replace the L15 to R563(0R3) for vendor request.
* SA - > SB: 14.Add 100K to PL the U70-74 to solve the wake on LAN.
1>Swap smart card connecter and use this one. P/N: 20.K0090.012 Page 18:
2>Dummy the 5 resisters of VGA: R46, R238, R240, R241, R242 - P/N:63.47234.151 15.Dummy BC38, R526, R527, R528 for vendor request.
3>Modify the U4-4 from 2D5V_S0 to 2D5V_S3 Page 19:
4>Change the Q6 from 2N7002 - P/N:84.27002.031 to TP0610 -P/N: 84.00610.031 , then swap D and S 16.Modify the 802.11L_ACT from CN18 pin12 to pin11.
5>Change R6 from 10K - 63.10334.151 to 1K - 63.10234.151 17.Use U91 as the gate to control PCIRST2# to 802.11 and PL 10K to PCIRST2#_80211
6>Connect R49 and R52 LVDSVDD to 2D5V_S3 18.Add 10K to pull up BAN_PME# to 3D3V_S5
7>Modify core voltage setting: (1)R313:100K->Dummy (2)R311:Dummy->1K (3)R325,R326:1K->Dummy (4)R328,R329:Dummy->100K Page 20:
8>Modify GPIO of KBC: (1)P20:HOTKEY->CHG_FLASH (2)P66:PCB_VER_SET2->EN_FLASH 19.Add 3 open-gapes for EMI request.
9>R403:33R(63.33034.1D1)->0R(63.R0034.1D1) Page 21:
10>Add U86 to modify the driving voltage from 3.3V to 5V 20.Add DC bias PH 4.7K to internal MIC
11>VGAU34: 71.00722.00U->71.00722.A0U Page 22:
* SB - > SC: 21.Update Audio Jack for ME request
Page 3: Page 23:
1> Reserve test pads for 48MSEL100/66# and DIV4# 22.Modify the email-led control method because there is no GND on KB for KB matrix to PL.
2> Change R418 to 0R and BC351 to dummy to tune 48M signal quality 23.Use 7474 to keep the reset of KBC while in S3.
Page 7: 24.Use the DTC124EKA and RB731U to prevent the leakage between KBC and Banister while in S3.
3> Change Page 24:
GPIO2 to MP_COMMAND, GPIO3 to MP_ACK, GPIO6 to OBLAN-80211#, GPIO20 to AD_OFF, GPIO29 to PCI_REQ#3, GPIO30 to PCI_GNT#3 25.Add helf smith-trigger to 5 button.
Page 11: Page 26:
4> Modify the logic of STD_LED and PWR_LED 26.Delet F2 and change it to 0.75A
5> Add R521 to pull 3D3V_S0 for SUSB# 27.Add Beads between USB conn. and bypass C for EMI request
Page 12: Page 27:
6> Change R269 pull H plane from 5V_S0 to 3D3V_S0 28.Use CC_CPUSTP to drive CC_DPSLP#
Page 13: 29.Change R93 from 0R to 4.7R for EMI request
7> Change HDD connecter for ME request Page 28:
8> Add pull H for PCI_REQ#3, PCI_GNT#3. and PCI_PERR# 30.Change R532 from 0R to 4.7R
Page 14: Page 29:
9> Change PCI_REQ# from 1 to 3 , PCI_GNT# from 1 to 3 31.Parallel 47KR to BC55
10> Add R546 between BAN_PME# and CARDBUS_PME# 32.For SKIP mode , modify the BC5 and BC140 to 47PF and add 100PF to replace R24 and R37.
Page 15: 33.Change R26,R27,R13 and R36 from 0R to 4.7R for EMI request.
11> Change the cardbus socket SKT3 for ME request Page 30:
Page 16: 34.Add smith trigger and debounce RC to solve 100uS drop of SUSC#
12> Change PLLVDD(Pin 1) to 3D3V_S0 Page 31:
13> Dummy Pin121~125 for 43AB21, but reserve resisters for 43AB22 35.Add bypass 0.1uF between AC Jack and bead for EMI request .
Page 17/18: 36.Change R3 from 10K to 2.2K
14> Mount the components for RTL8100BL Page 32:
15> Add R524 and Q32 for preventing leakage current 37.Change R97 from 15mR to 18mR for current limit of adaptor.
16> Modify JK2(RJ11-45) for ME request 38.Change R258 and R96 from 0R to 4.7R for EMI request
17> Add circuit for BIOS setting between LAN and 802.11 Page 33:
Page 19: 39.Add 10KR to Pull BL2# to 3D3V_S3
18> Add BC486 and BC488 for EMI request 40.Change R261 from 10K to 2.2K
Page 20/21/22: 41.Change U44 from MAX1615 to LP2951 for cost down
19> Add BEEP from uP to control BEEP sound Page 35:
20> Codec Pin 27: NC 42.DEL: K8, K9, K10, and K11
21> Add BC487 between AUD_GND and DIG_GND for EMI 43.Add: K15
22> Change U75 and U80 to GMT 1211
23> Change U77 to APA2020 SD -> SE
24> Performance tuing: Page 10:
(1) BC308 to 0.01UF (2)BC466, BC467, and BC469 to 3.3V (3)R491 to 470R (4)DUMMY:BC424, BC448, BC451, R506, R381, 1 Add F2 for safety request.
R383, BC475, BC476, BC434, BC432 (5)Change R513, R516, R497, R495 to 12K(6)Change R514, R496 to 15K (7)R498, R515 to Page 13:
27K (8)R382, R380 to 0R3 2.Remove R335 for the driving high is not enough.
Page 23: Page 27:
25> Modify KBC P27 to NC, P40 to EMAIL_LED#, P65 to BACKLIGHT_OFF# 3. Del R567
Page 24: Page 32:
26> Change button_interrupt from IRQ7 to PCI_INTB# 4.Change R97 from 64.R0185.A71 to 64.R0185781 because it might generate shortage due to the pad of compoment is too large
Page 28:
27> Reserve R532 for EMI request SE => -1
28> Add R531to pull L(Reduce_on) Page 7:
Page 29: 1. Change VCC of 82440MX from 3D3V_S0 to 3D3V_S3.
29> Change U3 and U36 to FDS6982S, then dummy D3 and D17 2. Change power plane of R139 from 5V_S0 to 5V_S3
30> Change D13 and D14 to 83.1R003.A8F 3. Change power plane of D9 from 3D3V_S0 to 3D3V_S3
Page 32: Page 20:
U9 -pin 13: NC 4. Reserve R569 and R570 to use different Codec.
Page 33: Page 22:
31> Modify the U48 circuit for preventing U48(5V) drive 82440MX(3V) 5. Tune R380, R381, R383, and R383 for audio performance. Wistron Corporation
32> Use U48 to replace U9(uP) to contorl charge_LED Page 30: 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Page 34: Taipei Hsien 221, Taiwan, R.O.C.
6. Add U21D between U35 and U60C.
33> Reserve test pads for clock-down circuit Title
TM100 Rev_History
Size Document Number Rev
C -1
TM100
Date: Thursday, April 04, 2002 Sheet 2 of 35
SA->SB Clock Generator CPU CLOCK = 440BX CLOCK + 877 MILS
440BX CLOCK = 1.25 ~ 1.35 inches
R403 0R2-0 3D3V_S0
6 14MGCL_D3 2 1
63.R0034.1D1
R405 33R2 CLK_3D3V_S0 2D5V_S0 CLK_3D3V_S0
1
1
1
7 14M_P4 2 1
2
1
63.33034.1D1 SB->SC R419 R412 R411
10KR2 10KR2 10KR2 R417 R402
R404 33R2 U65 TP32 63.10334.1D1 63.10334.1D1 63.10334.1D1 10KR2 DUMMY-R2
1 2 14MP4 1 28 R400 33R2 48MSEL100/66# 63.10334.1D1
7 PCLK_MX
2
2
2
63.33034.1D1 14M_IN REF0 VDDREF
2 27 14MVGA 1 2 14M_VGA 9
1
14M_OUT XTAL_IN REF1 63.33034.1D1 CPU_STOP#1
3 26 SPREAD#
2
XTAL_OUT SPREAD# R413 22R2 TP33
R421 33R2 PCLKMX 4 25
PCICLK_F VDDCPU DIV4#
9 PCLK_VGA 1 2 PCLKVGA 5 24 CLKCPUCLK0 1 2 CLK_CPUCLK0 4,7
63.33034.1D1 PCICLK1 CPUCLK0 63.22034.1D1
PCLKPCM 6 23
PCICLK2 CPUCLK1
7 22
VSSPCI VSSCPU D31 DUMMY-S1N4148
R420 33R2 8 21
VDDPCI VSSCORE
14 PCLK_PCM 1 2 PCLKLAN 9 20 CLK_PCI_STOP# 7 SUSA# 2 1 CLK_PWRDN#
63.33034.1D1 PCICLK3 PCI_STOP# 63.R0034.1D1 7 SUSA# ZZ.04148.011
PCLKMINI 10 19
PCLK1394 PCICLK4 VDDCORE
R424 33R2 11 18 CPU_STOP#1 1 R415 2 CC_CPUSTP# 6,27
PCICLK5 CPU_STOP# CLK_PWRDN# 0R2-0
17 PCLK_LAN 1 2 12 17
63.33034.1D1 EPCICLK PWRDWN# SPREAD#
13 16 DIV4# 1 2
VDD DIV4#
R423 33R2 48MSEL100/66# 14 15
USBCLK/SEL100/66# VSS48 R414 DUMMY-R2
19 PCLK_MINI 1 2
1
63.33034.1D1 ICS9248-61 ZZ.DUMMY.X02
R422 33R2 R401
16 PCLK_1394 1 2
63.33034.1D1 10KR2
63.10334.1D1
2
R418 0R2-0 SB->SC
7 48M_P4 1 2
63.R0034.1D1
R444 10R2
25 SIO_48M 1 2
63.10034.1D1
BC351
DUMMY-SC10P 3D3V_S0 CLK_3D3V_S0
BC333 SB->SC *Layout* 2D5V_S0
ZZ.10034.1B1
R442
1 2 14M_IN
0R3-0-U
20 mil
3D3V_S0
1 2
1
DUMMY-C3
X3 BC330
SC4D7U10V5ZY BC350 BC339 BC340 BC331 BC329 BC338
3D3V_S0 6,7,8,11,12,13,14,15,16,17,19,20,23,24,25,26,27,28,30,35 SCD1U SCD1U SCD1U SCD1U SCD1U SC4D7U10V5ZY
X-14.318MHZ-1 78.47593.411
2
78.10492.4B1 78.10492.4B1 78.10492.4B1 78.10492.4B1 78.10492.4B1 78.47593.411
BC332
2D5V_S0
1 2 14M_OUT
(PIN 28) (PIN 25)
DUMMY-C3
(PIN 8) (PIN 13) (PIN 19) near Chip Pin
2D5V_S0 4,28
SDRAM Clock Buffer 3D3V_S0
BC80 BC83 BC85 BC81
SCD1U SCD1U SCD1U SC4D7U10V5ZY
78.10492.4B1 78.10492.4B1 78.10492.4B1 78.47593.411
*Layout* 3D3V_S0 3D3V_S0
FS2 FS1 CLKA[1..4] CLKB[1..4] CLKOUT
OUTPUT PLL
DCLKIN longer than other 1
SOURCE SHUTDOWN
CLK (2.4inch) 0 0 TRISTATE TRISTATE DRIVEN PLL N
1
R108
R119 3D3V_S0 DUMMY-R2
0 1 DRIVEN TRISTATE DRIVEN PLL N
1KR2 ZZ.DUMMY.X02
63.10234.1D1 *1 0 REF Y
DRIVEN DRIVEN DRIVEN
2
2
U13 R114 22R2 DRIVEN DRIVEN DRIVEN PLL N
1 1
7 CLKDBUF 1 16 DCLKIN_R 2 1 DCLKIN 7
R121 10R2 REF CLKOUT R116 10R2 63.22034.1D1
2 15
CLKA1 CLKA4
8 CLK_SDRAM1 1 2 SDRAMCK1 3 14 SDRAMCK3 1 2 CLK_SDRAM3 8
63.10034.1D1 CLKA2 CLKA3 63.10034.1D1
4 13
R122 10R2 VDD VDD R115 10R2
5 12
GND GND
8 CLK_SDRAM0 1 2 SDRAMCK0 6 11 SDRAMCK2 1 2 CLK_SDRAM2 8
CLKB1 CLKB4
1
63.10034.1D1 7 10 63.10034.1D1
R125 CLKB2 CLKB3
8 9
56R3 FS2 FS1
63.56034.151 ICS9112BM-17
1
1
2
1
1
1
1
1
R120 BC82
R123 R124 DUMMY-R2 R107 DUMMY-C3 R118 R117
100KR2 100KR2 ZZ.DUMMY.X02 1KR2 100KR2 100KR2 Wistron Corporation
BC84 63.10434.1D1 63.10434.1D1 63.10234.1D1 63.10434.1D1 63.10434.1D1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
SC15P Taipei Hsien 221, Taiwan, R.O.C.
2
2
2
2
2
2
2
78.15034.1B1
Title
Clock Generator & SDRAM Clock Buffer
Size Document Number Rev
A3 -1
TM100
Date: Thursday, April 04, 2002 Sheet 3 of 35
VCC_CORE_S0
VCCT_S0 VCCT_S0 1D5V_S0
5,27 VCC_CORE_S0
5,28 1D5V_S0
VCCT_S0
1
1
1
R191 R251 R297 BC145
200R3 150R3 200R3 SCD1U
5,6,7,28 VCCT_S0
78.10492.4B1 VCC_CORE_S0
2
2
2
1
TP28 ITP_TDI
TPAD30 R174
56D2R3F U5A U5B
ZZ.PAD30.XXX
TP21 ITP_TDO 64.56R25.651
TPAD30 CPU_PICD0 AD19 D22
2
7 GTL_HA#[31..3] GTL_HD#[63..0] 7 PICD0 VCC_0
GTL_HA#3 K1 A16 GTL_HD#0 CPU_PICD1 AD17 F22
A3# D0# PICD1 VCC_1
1
TP15 ITP_TRST# GTL_HA#4 J1 B17 GTL_HD#1 CPU_PICCLK AF20 E21
A4# D1# PICCLK VCC_2
1
1
TPAD30 GTL_HA#5 G2 A17 GTL_HD#2 R185 H22
GTL_HA#6 A5# D2# 1KR3 R186 R175 VCC_3
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