Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer eMachines E520_E720_Compal_LA-4431P_Rev1.0
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A B C D E
1 1
Compal Confidential
2 2
KAWE0 M/B Schematics Document
Intel Penryn Processor with Cantiga + DDRII + ICH9M
3
2008-07-28 3
REV:1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4431
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401590
Date: Wednesday, July 30, 2008 Sheet 1 of 45
A B C D E
A B C D E
Compal Confidential
Intel Penryn Processor Thermal Sensor Clock Generator
Fan Control
Model Name : KAWE0 page 4
ADM7421ARMZ ICS9LPRS387
uPGA-478 Package page 4 page 16
File Name : LA-4431P
(Socket P) page 4,5,6
P/N : DA600009500 (RVE0)
1 1
P/N : DA600009510 (RVE1) FSB
H_A#(3..35) 667/800/1066MHz H_D#(0..63)
LCD Conn. CRT Conn.
page 17 page 18
Memory BUS(DDRII) 200pin DDRII-SO-DIMM X2
Intel Cantiga
Dual Channel BANK 0, 1, 2, 3 page 14,15
1.8V DDRII 533/667
LVDS uFCBGA-1329
page 7,8,9,10,11,12,13
Card Reader
JMB385 USB conn x2 Bluetooth CMOS
page 24 DMI C-Link
USB port 0, 2 Conn Camera
page 28 page 28 page 17
PCI-Express
2
Intel ICH9-M 3.3V 48MHz USB
2
3.3V 24.576MHz/48Mhz HD Audio
S-ATA
BGA-676
New Card MINI Card x1 LAN(GbE) page 19,20,21,22
Socket WLAN Realtek RTL8111C port 0 port 1
page 28 page 27 page 25 MDC 1.5 HDA Codec
Conn 31 ALC268
page page 32
SATA HDD CDROM
Conn.
page 23
Conn.
page 23
RJ45
page 26
Audio AMP
page 33
LPC BUS
3 3
ENE KB926 Phone Jack x3
RTC CKT. LS-4391P page 33
page 29
page 20 POWER/B Conn.
page 30
LS-4392P
Power On/Off CKT. Touch Pad Int.KBD
LID SW/B Conn. page 30 page 30
page 31 USB port 4
page 30
DC/DC Interface CKT. LS-4393P
LED/B Conn. BIOS
page 34 page 30
page 30
Power Circuit DC/DC
4
page 35,36,37,38 4
39,40,41,42
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4431
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401590
Date: Wednesday, July 30, 2008 Sheet 2 of 45
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails
Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
B+ AC or battery power rail for power circuit. N/A N/A N/A
1
S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF 1
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.05VS 1.05V switched power rail ON OFF OFF
+1.25VS 1.25V switched power rail ON OFF OFF
+1.5V 1.5V power rail for HDA ON ON OFF Board ID / SKU ID Table for AD channel
+1.5VS 1.5V switched power rail ON OFF OFF Vcc 3.3V +/- 5%
+1.8V 1.8V power rail for DDR ON ON OFF Ra/Rc/Re 100K +/- 5%
+1.8VS 1.8V switched power rail ON OFF OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+2.5VS 2.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+3VALW 3.3V always on power rail ON ON ON* 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+3V 3.3V power rail for SB ON ON X 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+3V_LAN 3.3V power rail for LAN ON ON X 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VS 3.3V switched power rail ON OFF OFF 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+5VALW 5V always on power rail ON ON ON* 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+5VS 5V switched power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+VSB VSB always on power rail ON ON ON* 7 NC 2.500 V 3.300 V 3.300 V
2 2
+RTCVCC RTC power ON ON ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
BOARD ID Table BTO Option Table
External PCI Devices Board ID PCB Revision BTO Item BOM Structure
Device IDSEL# REQ#/GNT# Interrupts
0 0.1
1 0.2
2 0.3
3 1.0
4 1A
5
6
7
8111C 8111C@
EC SM Bus1 address EC SM Bus2 address 8102E 8102E@
3 3
Device Address Device Address
Smart Battery 0001 011X b ADI ADT7421 1001 100X b
EEPROM(24C16/02) 1010 000X b
GMT G781-1 1001 101X b
ICH9M SM Bus address
Device Address
Clock Generator 1101 001Xb
(ICS9LPRS387, SLG8SP556V)
DDR DIMM0 1001 000Xb
DDR DIMM2 1001 010Xb
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4431
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401590
Date: Wednesday, July 30, 2008 Sheet 3 of 45
A B C D E
5 4 3 2 1
H_A#[3..35]
<7> H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2]
FAN1 Conn
<7> H_RS#[0..2]
JCPU1A +5VS
H_A#3 J4 H1 C10 10U_0805_10V4Z +5VS
A[3]# ADS# H_ADS# <7>
ADDR GROUP_0
H_A#4 L5 E2 H_BNR# <7> 1 2
H_A#5 A[4]# BNR#
D L4 A[5]# BPRI# G5 H_BPRI# <7> D
1
H_A#6 K5
H_A#7 A[6]# U2 D2
M3 A[7]# DEFER# H5 H_DEFER# <7>
H_A#8 N2 F21 1 8 1SS355_SOD323-2
A[8]# DRDY# H_DRDY# <7> VEN GND
H_A#9 J1 E1 2 7
A[9]# DBSY# H_DBSY# <7> VIN GND
H_A#10 N3 +VCC_FAN1 3 6
2
H_A#11 A[10]# EN_DFAN1 VSET VO GND D4
P5 A[11]# BR0# F1 H_BR0# <7> <29> EN_DFAN1 1 2 4 VSET GND 5
H_A#12 P2 R27 330_0402_5% 1 2
A[12]#
CONTROL
H_A#13 L2 D20 H_IERR# 1 G993P1UF_SOP8
H_A#14 A[13]# IERR# C427 BAS16_SOT23-3
P4 A[14]# INIT# B3 H_INIT# <20>
H_A#15 P1 0.01U_0402_16V7K C396
H_A#16 A[15]# 10U_0805_10V4Z
R1 A[16]# LOCK# H4 H_LOCK# <7> 2
Change to SA000022J00
<7> H_ADSTB#0 M1 ADSTB[0]# 20080227 1 2
C1 H_RESET# H_RESET# <7>
H_REQ#0 RESET# H_RS#0 +3VS C399
K3 REQ[0]# RS[0]# F3 20080430
H_REQ#1 H2 F4 H_RS#1 Add soft-start for +5VS drop issue 1000P_0402_50V7K
H_REQ#2 REQ[1]# RS[1]# H_RS#2
K2 REQ[2]# RS[2]# G3 1 2
1
H_REQ#3 J3 G2 H_TRDY# <7>
H_REQ#4 REQ[3]# TRDY# R299
L1 REQ[4]#
G6 10K_0402_5%
HIT# H_HIT# <7>
H_A#17 Y2 E4 40mil
A[17]# HITM# H_HITM# <7>
H_A#18 U5 JP12
2
H_A#19 A[18]# +VCC_FAN1
R3 A[19]# BPM[0]# AD4 1
ADDR GROUP_1
H_A#20 W6 AD3
A[20]# BPM[1]# <29> FAN_SPEED1 2
H_A#21 U4 AD1
H_A#22 A[21]# BPM[2]# 3
Y5 A[22]# BPM[3]# AC4 1
XDP/ITP SIGNALS
H_A#23 U1 AC2 C393 ACES_85205-03001
H_A#24 A[23]# PRDY# XDP_BPM#5 1000P_0402_50V7K CONN@
R4 A[24]# PREQ# AC1
H_A#25 T5 AC5 XDP_TCK
C H_A#26 A[25]# TCK XDP_TDI 2 C
T3 A[26]# TDI AA6
H_A#27 W2 AB3
H_A#28 A[27]# TDO XDP_TMS
W5 A[28]# TMS AB5
H_A#29 Y4 AB6 XDP_TRST#
H_A#30 A[29]# TRST# XDP_DBRESET#
U2 A[30]# DBR# C20 XDP_DBRESET# <21>
H_A#31 V4
H_A#32 A[31]# +1.05VS
W3 A[32]#
H_A#33 AA4 THERMAL
H_A#34 A[33]#
AB2 A[34]#
H_A#35 AA3 D21 H_PROCHOT#
A[35]# PROCHOT# H_THERMDA
<7> H_ADSTB#1 V1 ADSTB[1]# THERMDA A24
B25 H_THERMDC XDP_TDI R17 1 2 54.9_0402_1%
THERMDC
<20> H_A20M# A6 A20M#
ICH
ICH
<20> H_FERR# A5 FERR# THERMTRIP# C7 H_THERMTRIP# <8,20> left NC if no ITP
<20> H_IGNNE# C4 IGNNE# XDP_TMS R16 1 2 54.9_0402_1% 39Ohm
<20> H_STPCLK# D5 STPCLK#
C6 H CLK XDP_BPM#5 R8 1 2 54.9_0402_1%
<20> H_INTR LINT0
B4 A22 @
<20> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <16>
<20> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <16>
M4 H_PROCHOT# R32 2 1 56_0402_5%
RSVD[01]
N5 RSVD[02]
T2 H_IERR# R31 2 1 56_0402_5%
RSVD[03]
V3 RSVD[04]
RESERVED
B2 RSVD[05] Layout Note:
D2 RSVD[06]
D22 H_THERMDA&H_THERMDC Trace / Space = 10 / 10 mil
RSVD[07]
D3 RSVD[08]
B XDP_TRST# R13 54.9_0402_1% B
F6 RSVD[09] 2 1
XDP_TCK R7 1 2 54.9_0402_1%
Penryn
CONN@
+3VS
C95
0.1U_0402_16V4Z
1 2
+1.05VS U8
BSEL2 BSEL1 BSEL0 BCLK H_THERMDA
0 0 0 266 1 VDD SMCLK 8 EC_SMB_CK2 <29>
1
1
R39 C94 2 7
DP SMDATA EC_SMB_DA2 <29>
0 1 0 200 56_0402_5%
2200P_0402_50V7K
@ 3 DN ALERT# 6 1 2 +3VS
2 R541
2
0 1 1 166 4 5 10K_0402_5%
H_THERMDC THERM# GND
2
B
E
H_PROCHOT# 3 1 OCP# <21> EMC1402-1-ACZL-TR_MSOP8
A A
C
Q2
MMBT3904_SOT23-3
@
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2007/09/20 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATICS, MB A4431
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
401590
Date: Wednesday, July 30, 2008 Sheet 4 of 45
5 4 3 2 1
5 4 3 2 1
H_D#[0..63] JCPU1C
H_D#[0..63] <7>
+CPU_CORE A7 VCC[001] VCC[068] AB20 +CPU_CORE
JCPU1B A9 AB7
H_D#0 H_D#32 VCC[002] VCC[069]
E22 D[0]# D[32]# Y22 A10 VCC[003] VCC[070] AC7
D H_D#1 F24 AB24 H_D#33 A12 AC9 D
H_D#2 D[1]# D[33]# H_D#34 VCC[004] VCC[071]
E26 D[2]# D[34]# V24 A13 VCC[005] VCC[072] AC12
DATA GRP 0
H_D#3 G22 V26 H_D#35 A15 AC13
DATA GRP 2
H_D#4 D[3]# D[35]# H_D#36 VCC[006] VCC[073]
F23 D[4]# D[36]# V23 A17 VCC[007] VCC[074] AC15
H_D#5 G25 T22 H_D#37 A18 AC17
H_D#6 D[5]# D[37]# H_D#38 VCC[008] VCC[075]
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