Service Manuals, User Guides, Schematic Diagrams or docs for : acer Acer_Aspire_V3-771_VA70_BA52HR_CR
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5 4 3 2 1
VA70 BLOCK DIAGRAM POWER VGA POWER
CPU VCORE GPU VCORE
PAGE 80 PAGE 80
DDR3 1333/1600 MHz DDR-III SYSTEM, +3V, +5V +1.05VS_VGA
CPU channel A SO-DIMM*2 PAGE 81
PAGE 16
D
+VCCP & +VCCP_VT +1.5VS_VGA D
PAGE 82
Sandy Bridge DDR3 1333/1600 MHz
dGPU Ivy Bridge DDR-III DDR & VTT +3VS_VGA
PCIE X 16 channel B SO-DIMM*2 PAGE 83
N13P GS/GL/GT PAGE 17
2.5V & 1.5VS &1.1VS +12VS_VGA
PAGE 84
PAGE 3-10
PAGE 70~79 USB2.0
Camera SMART CHARGER LOAD SWITCH
FDI x 4 DMI x 4 PAGE 88 PAGE 91
POWER DETECT POWER PROTECT
HDMI PAGE 90 PAGE 92
PAGE 39 USB2.0
USB PORT9
LOAD SWITCH
CRT PAGE 91
PAGE 38
USB2.0 POWER PROTECT
LVDS/eDP USB PORT3 PAGE 92
PAGE 37
PCH PAGE 58
Head Phone Cougar Point USB2.0 Power Rails
Azalia Codec Azalia USB20 PORT1
(Combo Jack) Panther Point Sleep State RTC VA VSUS V VS
RTK/ALC271 (VB6) USB3.0 USB30 PORT2
S0 ON ON ON ON ON
C MIC C
PAGE 58
PAGE 41 42
HM77 USB2.0
USB20 PORT0
S3
S4
ON
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
K/B USB3.0 USB30 PORT1 S5/ AC ON ON ON OFF OFF
PAGE 48
PAGE 61 S5/ DC ON ON OFF OFF OFF
EC PAGE 30 LPC
T/P
PAGE 48 PCIE *1
HSPI MiniCard
FAN
IT8518E WLAN/WMAX PCIe Port
PAGE 49 PAGE 13-19 USB2.0 PCIE_P1 CARDREADER
BT combo
PAGE 55 PCIE_P2 Mini CARD (WLAN)
PCIE_P3 mSATA
USB30 IC FL1009 PCIE_P4 USB30
SPI ROM
SATA
PAGE 51 PCIE_P5
PCIE *1
4MB (BIOS/EC) PCIE_P6 LAN
PAGE 30
PCIE *1 Giga LAN
SPI AR8151/AR8152 RJ45 USB20 PORT
SPI ROM USB P00 External MB
PAGE 33 PAGE 34
2MB (ME) USB P01 External MB
PAGE 28 PCIE *1
Card Reader USB P02
B
RTS5209 USB P03 External DB
B
PAGE 40
SATA HDD USB P04
PAGE 60 USB P05 BT
PCIE *1
USB P08 Camera
mSATA/SSD
SATA HDD SATA 3.0 USB P09 External DB
PAGE 60 USB P10
PAGE 53
USB P11 SSD
SATA ODD USB P12
PAGE 60 USB P13
SATA PORT
PWR BOARD SATA P0 HDD 1
IO BOARD TP BT BOARD SATA P1 HDD 2
SATA P2 ODD 3
POWER Button
SATA P3 mSATA
USB PORT3
HP_OUT SATA P4
Touch PAD Button POWER LED SATA P5
A USB PORT9 A
MIC IN
LID SW
LID SW
Title : BLOCK DIAGRAM
BU1-RD Div.1-HW RD Dept.1 Engineer: Wing_Cheng
Size Project Name Rev
Custom
BA52HR/CR 1.0
Date: Friday, February 03, 2012 Sheet 1 of 77
5 4 3 2 1
5 4 3 2 1
BOM optional Remark
N/A For
/ABCT For ABCT
D D
/niAMT For no iAMT
/HOME For
/HR For Huron River
/Non_HSPI For ROM SETTING
Entry For
Main For
/USB20 For USB 2.0
/HSPI For
C /HDMI For HDMI
C
/TP1_AUD For power control
/TP1_BT For power control
/TP1_CAMERA For power control
/TP1_CR For power control
/TP1_LAN For power control
/TP1_ODD For power control
/TP1_WLAN For power control
/THERM For Palm Rest
B B
/usb30 For USB 3.0
/ZPODD For ODD battery saving
Mount R5108
@ For
@/MP For debug port, MP
/BT270 keypat list
/COMBO_BT keypat list
/SATA+ For Sata Repeater, SR
A A
Title : System Setting
PEGATRON COMPUTER INC Engineer: Wing_Cheng
Size Project Name Rev
A BA52HR/CR 1.0
Date: Friday, February 03, 2012 Sheet 2 of 94
5 4 3 2 1
5 4 3 2 1
+VCCP +VCCP 4,6,7,25,26,27,37,47,63,82
+VCCP
U0301A
PEG Compensation
J22 PEG_COMP R0301 1 1% 2 24.9Ohm
PEG_ICOMPI
J21
PEG_ICOMPO
22 DMI_TXN0 B27 H22
DMI_RX#[0] PEG_RCOMPO
22 DMI_TXN1 B25
DMI_RX#[1]
22 DMI_TXN2 A25 PCIENB_RXN[15:0] 70 Enable PCIE Lane Reversal
DMI_RX#[2] PCIENB_RXN15
22 DMI_TXN3 B24 K33
DMI_RX#[3] PEG_RX#[0]
PEG_RX#[1]
M35 PCIENB_RXN14 Need to PD CFG[2]
22 DMI_TXP0 B28 L34 PCIENB_RXN13
D DMI_RX[0] PEG_RX#[2] PCIENB_RXN12 D
22 DMI_TXP1 B26 J35
DMI_RX[1] PEG_RX#[3]
DMI
22 DMI_TXP2 A24 J32 PCIENB_RXN11
DMI_RX[2] PEG_RX#[4] PCIENB_RXN10
22 DMI_TXP3 B23 H34
DMI_RX[3] PEG_RX#[5] PCIENB_RXN9
H31
PEG_RX#[6] PCIENB_RXN8
22 DMI_RXN0 G21 G33
DMI_TX#[0] PEG_RX#[7] PCIENB_RXN7
22 DMI_RXN1 E22 G30
DMI_TX#[1] PEG_RX#[8] PCIENB_RXN6
22 DMI_RXN2 F21 F35
DMI_TX#[2] PEG_RX#[9] PCIENB_RXN5
22 DMI_RXN3 D21 E34
DMI_TX#[3] PEG_RX#[10] PCIENB_RXN4
E32
PEG_RX#[11] PCIENB_RXN3
22 DMI_RXP0 G22 D33
DMI_TX[0] PEG_RX#[12] PCIENB_RXN2
22 DMI_RXP1 D22 D31
DMI_TX[1] PEG_RX#[13] PCIENB_RXN1
F20 B33
PCI EXPRESS* - GRAPHICS
22 DMI_RXP2 DMI_TX[2] PEG_RX#[14]
22 DMI_RXP3 C21 C32 PCIENB_RXN0
DMI_TX[3] PEG_RX#[15]
PCIENB_RXP[15:0] 70
J33 PCIENB_RXP15
PEG_RX[0] PCIENB_RXP14
L35
PEG_RX[1] PCIENB_RXP13
22 FDI_TXN[7:0] K34
FDI_TXN0 PEG_RX[2] PCIENB_RXP12
A21 H35
FDI_TXN1 FDI0_TX#[0] PEG_RX[3] PCIENB_RXP11
H19 H32
FDI_TXN2 FDI0_TX#[1] PEG_RX[4] PCIENB_RXP10
E19 G34
FDI_TXN3 FDI0_TX#[2] PEG_RX[5] PCIENB_RXP9
Intel(R) FDI
F18 G31
FDI_TXN4 FDI0_TX#[3] PEG_RX[6] PCIENB_RXP8
B21 F33
FDI_TXN5 FDI1_TX#[0] PEG_RX[7] PCIENB_RXP7
C20 F30
FDI_TXN6 FDI1_TX#[1] PEG_RX[8] PCIENB_RXP6
D18 E35
FDI_TXN7 FDI1_TX#[2] PEG_RX[9] PCIENB_RXP5
E17 E33
FDI1_TX#[3] PEG_RX[10] PCIENB_RXP4
F32
PEG_RX[11] PCIENB_RXP3
22 FDI_TXP[7:0] D34
FDI_TXP0 PEG_RX[12] PCIENB_RXP2
A22 E31
FDI_TXP1 FDI0_TX[0] PEG_RX[13] PCIENB_RXP1
G19 C33
FDI_TXP2 FDI0_TX[1] PEG_RX[14] PCIENB_RXP0
E20 B32 PCIEG_RXN[15:0] 70
FDI_TXP3 FDI0_TX[2] PEG_RX[15]
G18
FDI_TXP4 FDI0_TX[3] PCIENB_TXN0 CX0301 0.22UF/10V /DGPU PCIEG_RXN15
B20 M29 2 1
FDI_TXP5 FDI1_TX[0] PEG_TX#[0] PCIENB_TXN1 CX0302 0.22UF/10V /DGPU PCIEG_RXN14
C19 M32 2 1
FDI_TXP6 FDI1_TX[1] PEG_TX#[1] PCIENB_TXN2 CX0303 0.22UF/10V /DGPU PCIEG_RXN13
D19 M31 2 1
FDI_TXP7 FDI1_TX[2] PEG_TX#[2] PCIENB_TXN3 CX0304 0.22UF/10V /DGPU PCIEG_RXN12
F17 L32 2 1
FDI1_TX[3] PEG_TX#[3] PCIENB_TXN4 CX0305 0.22UF/10V /DGPU PCIEG_RXN11
L29 2 1
PEG_TX#[4] PCIENB_TXN5 CX0306 0.22UF/10V /DGPU PCIEG_RXN10
22 FDI_FSYNC0 J18 K31 2 1
FDI0_FSYNC PEG_TX#[5] PCIENB_TXN6 CX0307 0.22UF/10V /DGPU PCIEG_RXN9
C 22 FDI_FSYNC1 J17 K28 2 1 C
FDI1_FSYNC PEG_TX#[6] PCIENB_TXN7 CX0308 0.22UF/10V /DGPU PCIEG_RXN8
J30 2 1
PEG_TX#[7] PCIENB_TXN8 CX0309 0.22UF/10V /DGPU PCIEG_RXN7
22 FDI_INT H20 J28 2 1
FDI_INT PEG_TX#[8] PCIENB_TXN9 CX0310 0.22UF/10V /DGPU PCIEG_RXN6
H29 2 1
PEG_TX#[9] PCIENB_TXN10 CX0311 0.22UF/10V /DGPU PCIEG_RXN5
22 FDI_LSYNC0 J19 G27 2 1
FDI0_LSYNC PEG_TX#[10] PCIENB_TXN11 CX0312 0.22UF/10V /DGPU PCIEG_RXN4
22 FDI_LSYNC1 H17 E29 2 1
FDI1_LSYNC PEG_TX#[11] PCIENB_TXN12 CX0313 0.22UF/10V /DGPU PCIEG_RXN3
F27 2 1
PEG_TX#[12] PCIENB_TXN13 CX0314 0.22UF/10V /DGPU PCIEG_RXN2
D28 2 1
+VCCP PEG_TX#[13] PCIENB_TXN14 CX0315 0.22UF/10V /DGPU PCIEG_RXN1
F26 2 1
PEG_TX#[14] PCIENB_TXN15 CX0316 0.22UF/10V /DGPU PCIEG_RXN0
DP Compensation PEG_TX#[15]
E25 2 1
24.9Ohm 2 1% 1 R0302 DP_COMP A18 PCIEG_RXP[15:0] 70
eDP_COMPIO PCIENB_TXP0 CX0317 0.22UF/10V /DGPU PCIEG_RXP15
A17 M28 2 1
eDP_ICOMPO PEG_TX[0] PCIENB_TXP1 CX0318 0.22UF/10V /DGPU PCIEG_RXP14
37 DP_HPD#_PCH B16 M33 2 1
eDP_HPD PEG_TX[1] PCIENB_TXP2 CX0319 0.22UF/10V /DGPU PCIEG_RXP13
M30 2 1
PEG_TX[2] PCIENB_TXP3 CX0320 0.22UF/10V /DGPU PCIEG_RXP12
L31 2 1
PEG_TX[3] PCIENB_TXP4 CX0321 0.22UF/10V /DGPU PCIEG_RXP11
37 DP_AUXP_PCH C15 L28 2 1
eDP_AUX PEG_TX[4] PCIENB_TXP5 CX0322 0.22UF/10V /DGPU PCIEG_RXP10
37 DP_AUXN_PCH D15 K30 2 1
eDP_AUX# PEG_TX[5]
eDP
K27 PCIENB_TXP6 CX0323 2 1 0.22UF/10V /DGPU PCIEG_RXP9
PEG_TX[6] PCIENB_TXP7 CX0324 0.22UF/10V /DGPU PCIEG_RXP8
J29 2 1
PEG_TX[7] PCIENB_TXP8 CX0325 0.22UF/10V /DGPU PCIEG_RXP7
37 DP_TXP0_PCH C17 J27 2 1
eDP_TX[0] PEG_TX[8] PCIENB_TXP9 CX0326 0.22UF/10V /DGPU PCIEG_RXP6
37 DP_TXP1_PCH F16 H28 2 1
T0301 DP_TXP2_PCH eDP_TX[1] PEG_TX[9] PCIENB_TXP10 CX0327 0.22UF/10V /DGPU PCIEG_RXP5
1 C16 G28 2 1
T0302 DP_TXP3_PCH eDP_TX[2] PEG_TX[10] PCIENB_TXP11 CX0328 0.22UF/10V /DGPU PCIEG_RXP4
1 G15 E28 2 1
eDP_TX[3] PEG_TX[11] PCIENB_TXP12 CX0329 0.22UF/10V /DGPU PCIEG_RXP3
F28 2 1
PEG_TX[12] PCIENB_TXP13 CX0330 0.22UF/10V /DGPU PCIEG_RXP2
37 DP_TXN0_PCH C18 D27 2 1
eDP_TX#[0] PEG_TX[13] PCIENB_TXP14 CX0331 0.22UF/10V /DGPU PCIEG_RXP1
37 DP_TXN1_PCH E16 E26 2 1
T0303 DP_TXN2_PCH eDP_TX#[1] PEG_TX[14] PCIENB_TXP15 CX0332 0.22UF/10V /DGPU PCIEG_RXP0
1 D16 D25 2 1
T0304 DP_TXN3_PCH eDP_TX#[2] PEG_TX[15]
1 F15
eDP_TX#[3]
SOCKET989
12V013ISM000 If Support PCIE Gen3, change AC Cap to 0.22uF
1201-006D000 - 988B for Huron River
B B
A A
Title : CPU(1)_DMI,PEG,FDI,CLK,MISC
PEGATRON COMPUTER INC Engineer: Wing_Cheng
Size Project Name Rev
C BA52HR/CR 1.0
Date: Friday, February 03, 2012 Sheet 3 of 94
5 4 3 2 1
5 4 3 2 1
Select the termination voltage of DMI and FDI Tx/Rx (PCH Strap) U0301B
+1.5V_VCCDDQ +1.5V_VCCDDQ 7
H_SNB_IVB# connected to DF_TVS via 1Kohm
DF_TVS needs PU via 2.2Kohm to +1.8VS CLK_EXP_P_R SP0404 1
+3VS +3VS 16,17,20,21,22,23,24,25,26,27,28,30,37,38,39,40,41,47,48,49,53,55,60,63,66,69,91,92
A28 2 R0402 CLK_EXP_P 21
MISC
BCLK
CLOCKS
C26 A27 CLK_EXP_N_R SP0405 1 2 R0402 +3VSUS
25 H_SNB_IVB# SNB_IVB# BCLK# CLK_EXP_N 21 +3VSUS 22,24,27,28,30,33,65,81,85,92
1 2 +VCCP +VCCP 3,6,7,25,26,27,37,47,63,82
T0401 1 TP_SKTOCC#_R AN34 R0431 1KOhm
SKTOCC# CLK_DP_P_R RN0401B
A16 @ 3 0Ohm 4 CLK_DP_P 21 +3V +3V 24,37,51,63,65,91
DPLL_REF_SSCLK CLK_DP_N_R RN0401A
A15 1 0Ohm 2 CLK_DP_N 21
DPLL_REF_SSCLK#
R0430 1KOhm
T0402 1 TP_CATERR#_R AL33 1 2 +VCCP
CATERR#
do not remove because POWER removed thier PU R. Joyoung0613
THERMAL
DDR3 DRAM Reset. @
25 H_PECI AN33 R8 CPUDRAMRST# 5
D PECI SM_DRAMRST# D
DDR3
MISC
+VCCP 62Ohm 2 1 R0404
R0403 System Memory Impedance Compe◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo