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A B C D E
Compal Confidential
Model Name : V5WE2/T2 (EA/EG50_HW)
File Name : LA-9531P
1 1
Compal Confidential
2 2
EA50_HW M/B Schematics Document
Intel Shark Bay ULT (Hasswell + Lynx Point-LP)
AMD SUN
3 2012-09-24 3
REV:0.1
4 4
ZZZ
Part Number Description Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
DA60000XL00 PCB 0VR LA-9531P REV0 M/B
Issued Date Deciphered Date Cover Page
V5WE2_PCB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, September 25, 2012 Sheet 1 of 50
A B C D E
A B C D E
CRT Conn.
Fan Control
page 27 page 36
DP to VGA HDMI Conn. eDP Conn.
1 1
ITE IT6511FN page 25 page 24
204pin DDR3L-SO-DIMM X1
page 26
eDP
Intel Haswell ULT BANK 0, 1, 2, 3 page 15
DP x 2 lanes HDMI x 4 lanes Memory BUS
2.7GT/s 2.97GT/s Dual Channel
DDI
Haswell ULT
Processor 1.35V DDR3L 1333/1600 204pin DDR3L-SO-DIMM X1
BANK 4, 5, 6, 7 page 16
MINI Card AMD SUN OPI
WLAN with DDR3 x4
USB port 8 page 30 page 17~23
PCIe 2.0 PCIe 2.0 x4 USB 3.0 USB 2.0 CMOS
5GT/s 5GT/s conn x1 conn x2 Camera
2
port 4 port 5
Lynx Point - LP USB port 0 USB/B (port 1,2) USB port 5
2
Flexible IO
page 32 page 32 page 24
PCH
PCIe 2.0 48MHz
5GT/s USBx8
SATA3.0 SATA3.0
port 3 6.0 Gb/s 6.0 Gb/s
port 0 port 2 HD Audio 3.3V 24MHz
LAN(GbE) SATA HDD SATA CDROM
Boardcom Conn. Conn. HDA Codec
57786Xpage 1168pin BGA ALC3225
38 page 31 page 31
page 04~14 page 35
SPI
3
Card Reader LPC BUS 3
2 in 1 SPI ROM x2
(SD/MMC) CLK=24MHz Int. Speaker Int. MIC Combo Jack
page 29 page 7
ENE page 35 page 35 page 35
KB9012/KB932
page 33
RTC CKT. Sub Board
page 6
Touch Pad Int.KBD
LS-5931P page 34 page 34
Power On/Off CKT. PWR/B
page 32
page 34
LS-5932P EC ROM x1
4
DC/DC Interface CKT. USB/B (port 1,2) (KB932) 33
4
page
page 37 page 32
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Power Circuit DC/DC Issued Date Deciphered Date Block Diagrams
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
page 38~38 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, September 25, 2012 Sheet 2 of 50
A B C D E
A B C D E
SIGNAL
STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Voltage Rails Full ON HIGH HIGH HIGH HIGH ON ON ON ON
Power Plane Description S1 S3 S5 S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
VIN Adapter power supply (19V) N/A N/A N/A
S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF
BATT+ Battery power supply (12.6V) N/A N/A N/A
B+ AC or battery power rail for power circuit. N/A N/A N/A S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
1 1
+CPU_CORE Core voltage for CPU ON OFF OFF
S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+VGA_CORE Core voltage for GPU ON OFF OFF
+0.675VS +0.675VSP to +0.675VS switched power rail for DDR terminator ON OFF OFF Board ID / SKU ID Table for AD channel
+1.05VSDGPU +1.0VSDGPU switched power rail for GPU ON OFF OFF Vcc 3.3V +/- 5%
+0.95VSDGPU +0.95VSDGPUP to +0.95VSDGPU switched power rail for CPU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.35V +1.35VP to +1.35V power rail for DDRIIIL ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS +1.5V to +1.5VS switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+1.5VSDGPU +1.5VSDGPUP to +1.5VSDGPU switched power rail for GPU ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+1.8VS +3VS to 1.8V switched power rail to CPU ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V
+1.8VSDGPU +1.8VS to +1.8VSDGPU switched power rail for GPU ON OFF OFF 3 33K +/- 5% 0.712 V 0.819 V 0.875 V
+3VALW +3VALW always on power rail ON ON ON* 4 56K +/- 5% 1.036 V 1.185 V 1.264 V
+3VLP B+ to +3VLP power rail for suspend power ON ON ON 5 100K +/- 5% 1.453 V 1.650 V 1.759 V
+3VS +3VALW to +3VS power rail ON OFF OFF 6 200K +/- 5% 1.935 V 2.200 V 2.341 V
+3VSDGPU +3VS to +3VSDGPU switched power rail for GPU ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V
+5VALW +5VALWP to +5VALW power rail ON ON ON*
+5VS +5VALW to +5VS switched power rail ON OFF OFF
BOARD ID Table BTO Option Table
2 2
+VSB +VSBP to +VSB always on power rail for sequence control ON ON ON* BTO Item BOM Structure
+RTCVCC RTC power ON ON ON Board ID PCB Revision Unpop @
0 0.1 Connector CONN@
1 0.2 EC 932 932@
2 0.3 EC 9012 9012@
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF. 3 1.0 W/Charger CHR@
4 WO/Charger NCHR@
EC SM Bus1 address EC SM Bus2 address 5 Analog MIC AMIC@
6 Digital MIC DMIC@
Device Address Device Address
Smart Battery 0001 011X On Board Thermal Senser 0100 110x
7
VGA Internal Thermal Senser 0100 000x
AMD GPU VGA@
USB Port Table Mars component MARS@
G Senser 0011 000x
3 External VRAM Selection X76@
PCH SM Bus address USB 2.0 Port
USB Port VRAM x 8pcs 128@
0 USB Port(Left 3.0)
Device Address
ChannelA DIMM0 1001 000x JDIMM1
1 USB Port(Right 2.0) TPM Module TPM@
3 3
ChannelB DIMM1 1001 010x JDIMM2
2 USB Port(Right 2.0) G-Sensor GSEN@
3 KB Backlight BL@
EHCI1
4 Mini Card (WLAN+BT)
5
6 XDP (Debug Port) XDP@
7 Camera Debug Only DEG@
USB 3.0 Port
0 USB Port(Left 3.0)
1
4 XHCI 4
2
3
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/07/10 2013/07/10 Title
Issued Date Deciphered Date Notes List
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
V5WE2 M/B LA-9531P Schematic
Date: Tuesday, September 25, 2012 Sheet 3 of 50
A B C D E
5 4 3 2 1
HASWELL_MCP_E
U1A
C54 C45
26 CPU_DP1_N0 DDI1_TXN0 EDP_TXN0 EDP_TXN0 24
C55 B46
26 CPU_DP1_P0 DDI1_TXP0 EDP_TXP0 EDP_TXP0 24
B58 A47
26 CPU_DP1_N1 DDI1_TXN1 EDP_TXN1 EDP_TXN1 24
C58 B47
DP to CRT 26 CPU_DP1_P1
B55 DDI1_TXP1
DDI1_TXN2
EDP_TXP1 EDP_TXP1 24
A55 C47
A57 DDI1_TXP2 EDP_TXN2 C46
B57 DDI1_TXN3 EDP_TXP2 A49
DDI1_TXP3 DDI EDP EDP_TXN3 B49
D D
C51 EDP_TXP3
25 CPU_DP2_N0 DDI2_TXN0
C50 A45 EDP_AUXN 24
25 CPU_DP2_P0 DDI2_TXP0 EDP_AUXN
C53 B45 EDP_AUXP 24
25 CPU_DP2_N1 DDI2_TXN1 EDP_AUXP
B54
HDMI 25
25
CPU_DP2_P1
CPU_DP2_N2
C49 DDI2_TXP1
DDI2_TXN2 EDP_RCOMP
D20 EDP_COMP R1 1 2 24.9_0402_1% +VCCIOA_OUT
B50 A43 Trace width=20 mils,Spacing=25mil,Max length=100mils
25 CPU_DP2_P2 DDI2_TXP2 EDP_DISP_UTIL
A53
25 CPU_DP2_N3 DDI2_TXN3
B53
25 CPU_DP2_P3 DDI2_TXP3 EDP_DISP_UTIL 24
1 OF 19 Rev1p2
Reserved for ESD
XDP_PRDY#_R C63 @1 2 6.8P_0402_50V8C
Reserved for ESD XDP_PREQ#_R C64 @1 2 6.8P_0402_50V8C
HASWELL_MCP_E
U1B XDP_TCK_R C96 @1 2 6.8P_0402_50V8C
XDP_TMS_R C97 @1 2 6.8P_0402_50V8C
C94 @1 2 6.8P_0402_50V8C XDP_TRST#_R C98 @1 2 6.8P_0402_50V8C
T20 @ D61
T2 @ K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY#_R R27 1 XDP@ 2 0_0402_5% XDP_PRDY#
+1.35V 33 H_PECI PECI PRDY K62 XDP_PREQ#_R R28 1 XDP@ 2 0_0402_5% XDP_PREQ#
2 1 R68 R8 JTAG
PREQ E60 XDP_TCK_R R29 1 XDP@ 2 0_0402_5% XDP_TCK
+1.05VS_VTT PROC_TCK
62_0402_5% 56_0402_5% E61 XDP_TMS_R R30 1 XDP@ 2 0_0402_5% XDP_TMS
1 2 H_PROCHOT#_R K63 PROC_TMS E59 XDP_TRST#_R R31 1 XDP@ 2 0_0402_5% XDP_TRST#
33,38,39 H_PROCHOT# PROCHOT PROC_TRST
THERMAL F63 XDP_TDI_R R20 1 XDP@ 2 0_0402_5% XDP_TDI
PROC_TDI
1
C C95 @1 2 6.8P_0402_50V8C F62 XDP_TDO_R R21 1 XDP@ 2 0_0402_5% XDP_TDO C
R184 Reserved for ESD PROC_TDO
470_0603_5% R6 1 2 10K_0402_5% H_CPUPW RGD C61
PROCPWRGD PWR
C60 @1 2 6.8P_0402_50V8C J60 XDP_BPM#0_R R22 1 XDP@ 2 0_0402_5% XDP_OBS0
2
BPM#0 H60 XDP_BPM#1_R R23 1 XDP@ 2 0_0402_5% XDP_OBS1
Reserved for ESD BPM#1 H61 @ T148
DIMM_DRAMRST# BPM#2 H62 @ T149
DIMM_DRAMRST# 15,16 BPM#3
R11 1 2 200_0402_1% SM_RCOMP0 AU60 K59 @ T150
R13 1 2 120_0402_1% SM_RCOMP1 AV60 SM_RCOMP0 DDR3 BPM#4 H63 @ T151
R41 1 2 100_0402_1% SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 @ T152
DIMM_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 @ T153
DDR_PG_CTRL AV61 SM_DRAMRST BPM#7
15 DDR_PG_CTRL SM_PG_CNTL1
DDR3 Compensation Signals
2 OF 19 Rev1p2
+1.05VS_VTT +1.05VS_VTT
Reserved for ESD
PU/PD for JTAG signals JXDP1 CONN@
1 2
6.8P_0402_50V8C 2 1@ C92 XDP_PREQ# 3 GND0 GND1 4 CFG17
+3VS OBSFN_A0 OBSFN_C0 CFG17 14
6.8P_0402_50V8C 2 1@ C93 XDP_PRDY# 5 6 CFG16
OBSFN_A1 OBSFN_C1 CFG16 14
7 8
B CFG0 9 GND2 GND3 10 CFG8 B
14 CFG0 OBSDATA_A0 OBSDATA_C0 CFG8 14
CFG1 11 12 CFG9
+3VALW _PCH 14 CFG1 OBSDATA_A1 OBSDATA_C1 CFG9 14
XDP_DBRESET# R3 1 @ 2 1K_0402_5% 13 14
CFG2 15 GND4 GND5 16 CFG10
14 CFG2 OBSDATA_A2 OBSDATA_C2 CFG10 14
1 XDP@ 2 CFG3_R 17 18 CFG11
+1.05VS_VTT 14 CFG3 OBSDATA_A3 OBSDATA_C3 CFG11 14
R25 1K_0402_1% 19 20
GND6 GND7
1
XDP_OBS0 21 22 CFG19
OBSFN_B0 OBSFN_D0 CFG19 14
R4 XDP_OBS1 23 24 CFG18
OBSFN_B1 OBSFN_D1 CFG18 14
1K_0402_5% 25 26
XDP_TMS R86 1 @ 2 51_0402_5% CFG4 27 GND8 GND9 28 CFG12
@ 14 CFG4 OBSDATA_B0 OBSDATA_D0 CFG12 14
CFG5 29 30 CFG13
14 CFG5 CFG13 14
2
XDP_TDI R87 1 XDP@ 2 51_0402_5% 31 OBSDATA_B1 OBSDATA_D1 32
SYS_PW ROK_XDP CFG6 33 GND10 GND11 34 CFG14
14 CFG6 OBSDATA_B2 OBSDATA_D2 CFG14 14
XDP_PREQ# R88 1 @ 2 51_0402_5% CFG7 35 36 CFG15
14 CFG7 OBSDATA_B3 OBSDATA_D3 CFG15 14
37 38
XDP_TDO R89 1 XDP@ 2 51_0402_5% H_CPUPW RGD 1K_0402_5% 1 XDP@ 2 R5 H_CPUPW RGD_XDP 39 GND12 GND13 40
PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_ITP 7
8 PBTN_OUT#_R 0_0402_5% 1 XDP@ 2 R14 CFD_PW RBTN#_XDP 41 42 CLK_CPU_ITP# 7
43 HOOK1 ITPCLK#/HOOK5 44
0_0402_5% 1 XDP@ 2 R15 CPU_PW R_DEBUG_R 45 VCC_OBS_AB VCC_OBS_CD 46 XDP_RST#_R R7 1 XDP@ 2 1K_0402_5%
11 CPU_PW R_DEBUG HOOK2 RESET#/HOOK6 PLT_RST# 33,34,8
XDP_TCK R90 1 XDP@ 2 51_0402_5% 8 SYS_PW ROK 0_0402_5% 1 XDP@ 2 R16 SYS_PW ROK_XDP 47 48 XDP_DBRESET#_R R19 1 XDP@ 2 0_0402_5%
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