Service Manuals, User Guides, Schematic Diagrams or docs for : asus A7J
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5 3 2 1
CLOCK GEN CPU CORE POWER
ICS 954310 IMVP-6
CPU Page 28 Page ?
D YONAH MEROM D
31W 35W THERMAL SENSOR
& FAN CONTROL SYSTEM POWER
Page 3,4
DVI
DVI-D PSB Page 5 Page ?
Page ? 667MHz
LVDS
LCD
Page ?
NORTH DDR2 SO-DIMM0
TV-OUT TV ATIM56P BRIDGE DDR2 TOP Page 21
DDR2
Page ? DDR2 256MB Intel 945GM TERMINATION
18~20W Page 23
CRT
RGB 8~8.5W DDR2 SO-DIMM1
Page BOT Page 22
Page ? 13,14,15,16,17,18
Page
C 6,7,8,9,10,11,12 C
1394 x4 DMI
Card
R5C832 PCI IDE
Reader
Page 37,38
MASTER-HDD
SOUTH Page 39
TV-Tunner BRIDGE ODD
Page 29 ICH7-M
2W
AZALIA AUDIO AMP
CIR SUPER I/O LPC AZALIA CODEC Page ?
ITEIT8705 Page Realtek ALC882H
B Page 34,35,36 B
Page 42 24,25,26,27 AUDIO JACK & MIC
SIR Page ?
MDC MODEM
AUDIO DJ KEY Page 33
EC RJ11 &
IT8510E RJ45
Page 40 CONN.
INSTANT KEY
ISA PCIE x1 GIGALAN
A7J
Page ?
RTL8111B Page 32
FWH BIOS USB
Page 41
USB2.0 x5 PCIE x1
Page 43
MINICARD Page 30
A
CMOS USB PCIE x1
A
Camera USB NEWCARD Page 31
Page 19
Title : BLOCK DIAGRAM
USB Engineer Mark , Frank
Blue Tooth ASUSTeK COMPUTER INC. NB1
Size Project Name Rev
Custom A7J 2.0
Page 46 Date Tuesday November 29 2005 Sheet 1 of 52
5 3 2 1
A B C D E
POWER INTERFACE IMPEDENCE PCB STACK-UP
REVISION LIST SIGNALS TYPE POWER PCB THICKNESS: 1.6 mm
Single-Ended
R1.0 2005/08/01
L1 TOP
PM_PSI# O +VCCP 27.4 OHM WIDTH
L2 GND
1 R1.1 2005/10/20 VR_VID[5:0] O +VCCP TOP/BOT 18 mils 1
L3 IN1
VRON O +3.3V
L4 VCC
R2.0 2005/11/17 PM_DPRSLPVR O +3.3V 37.5 OHM WIDTH
L5 IN2
CPU_STP# O +3.3V TOP/BOT 11 mils
IN1/IN2/IN3 11 mils L6 IN3
R2.1 2005/11/25 RST_BTN# O +3.3V
L7 GND
CLK_EN# I +3.3V 42 OHM WIDTH
L6 BOT
DELAY_VR_PWRGD I +3.3V TOP/BOT 9 mils
OTP_RESET# I +3.3V IN1/IN2/IN3 9 mils
SHUT_DOWN# I +3.3V 50 OHM WIDTH
BAT_LEARN I +3.3V TOP/BOT 6.5 mils
BAT_LLOW#_OC I +3.3V IN1/IN2/IN3 6.5 mils
2
BAT1_IN#_OC I +3.3V 55 OHM WIDTH 2
BAT2_IN#_OC I +3.3V TOP/BOT 5 mils
CHG_EN_OC I +3.3V IN1/IN2/IN3 5 mils
CHG_LED I +3.3V 75 OHM WIDTH
SMCLK_BAT1 IO +3.3V TOP/BOT 4 mils
SMDATA_BAT1 IO +3.3V IN1/IN2/IN3 4 mils
SMCLK_BAT2 IO +3.3V Differential
SMDATA_BAT2 IO +3.3V 70 OHM WIDTH/SPACE
SUSB# O +3.3V TOP/BOT 9 mils/ 4 mils
SUSC# O +3.3V IN1/IN2/IN3 9 mils/ 4 mils
1.8V_PWRGD I +3.3V 85 OHM WIDTH/SPACE
1.5VS_PWRGD I +3.3V TOP/BOT 5 mils/ 4 mils
3 VSUS_ON O +3.3V IN1/IN2/IN3 5 mils/ 4 mils 3
ACIN_OC I +3.3V 90 OHM WIDTH/SPACE
ACIN# I AC_BAT_SYS TOP/BOT 5 mils/ 4.5 mils
+3VA PWR +3.3V IN1/IN2/IN3 5 mils/ 4.5 mils
+5VA PWR +5V 100 OHM WIDTH/SPACE
+5VLCM PWR +5VLCM TOP/BOT 5 mils/ 7 mils
A/D_DOCK_IN PWR DC IN1/IN2/IN3 5 mils/ 7 mils
AC_BAT_SYS PWR DC 110 OHM WIDTH/SPACE
TOP/BOT 4 mils/ 8 mils
IN1/IN2/IN3 4 mils/ 8 mils
POWER PLANE
POWER VOLTAGE CURRENT
4 +VCORE 0.7 - 1.77V 27A PCI INTERFACE 4
+VCCP 1.05 V 6.0A
PCI_REQ#
+0.9VS 0.9V 1.0A
+1.5VS 1.5V 3A MINIPCI(TV) PCI_REQ#0
+1.8V 1.8V 5.5A CB&1394 PCI_REQ#1
+1.8VS 1.8V 3.3A
+2.5VS 2.5V 0.3 A
+3V 3.3V 1.5A
IDSEL
+3VS 3.3V 2.0A
+3VSUS 3.3V 0.72A MINIPCI(TV) PCI_AD16
+5V 5V 4.8A CB&1394 PCI_AD17
5
+5VS 5V 3.3A 5
+5VSUS 5V 0.01A
+12V 12V 0.25A Title : BLOCK DIAGRAM
+12VS 12V 0.25A Engineer Mark , Frank
ASUSTeK COMPUTER INC. NB1
Size Project Name Rev
Custom A7J 2.0
Date: Tuesday, November 29, 2005 Sheet 2 of 52
A B C D E
5 3 2 1
D TPC28T 1 T188 D
U1A
6 H_A#[16 3] U1B
H A#3 J4 H1
A[3]# ADS# H_ADS# 6 6 H_D#[15 0] H_D#32 H_D#[47 32] 6
H A#4 L4 E2 H D#0 E22 AA23
A[4]# BNR# H_BNR# 6 D[0]# D[32]# H_D#33
H_A#5 M3 G5 +VCCP_AGTL+ H_D#1 F24 AB24
A[5]# BPRI# H_BPRI# 6 D[1]# D[33]# H D#34
H A#6 K5 H D#2 E26 V24
H A#7 A[6]# H D#3 D[2]# D[34]# H_D#35
M1 A[7]# DEFER# H5 H_DEFER# 6 H22 D[3]# D[35]# V26
1
ADDR GROUP 0
DATA GRP 2
H_A#8 N2 F21 H_D#4 F23 W25 H_D#36
A[8]# DRDY# H_DRDY# 6 D[4]# D[36]#
DATA GRP 0
H_A#9 J1 E1 R1 H_D#5 G25 U23 H_D#37
H_A#10 A[9]# DBSY# H_DBSY# 6 D[5]# D[37]# H_D#38
N3 H D#6 E25 U25
H_A#11 A[10]# 56Ohm H_D#7 D[6]# D[38]# H_D#39
P5 A[11]# BR0# F1 H_BR0# 6 E23 D[7]# D[39]# U22
H_A#12 P2 H_D#8 K24 AB25 H_D#40
H A#13 A[12]# H_IERR# H D#9 D[8]# D[40]# H_D#41
2
L1 D20 G24 W22
CONTROL
H A#14 A[13]# IERR# H_D#10 D[9]# D[41]# H_D#42
P4 A[14]# INIT# B3 H_INIT# 24 J24 D[10]# D[42]# Y23
H_A#15 P1 H_D#11 J23 AA26 H_D#43
H A#16 A[15]# H D#12 D[11]# D[43]# H_D#44
R1 A[16]# LOCK# H4 H_LOCK# 6 H26 D[12]# D[44]# Y26
L2 H D#13 F26 Y22 H_D#45
6 H_ADSTB#0 ADSTB[0]# D[13]# D[45]# H_D#46
B1 H_CPURST# H_D#14 K22 AC26
6 H_REQ#[4 0] H_REQ#0 RESET# H_RS#0 H_CPURST# 6 H_CPURST# D[14]# D[46]# H_D#47
K3 F3 1 T193 H D#15 H25 AA24
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_RS#0 6 D[15]# D[47]#
H2 F4 TPC28T H23 W24
REQ[1]# RS[1]# H_RS#2 H_RS#1 6 6 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 6
H_REQ#2 K2 G3 G22 Y25
H_REQ#3 REQ[2]# RS[2]# H_RS#2 6 6 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 6
J3 REQ[3]# TRDY# G2 H_TRDY# 6 6 H_DINV#0 J26 DINV[0]# DINV[2]# V23 H_DINV#2 6
H_REQ#4 L5 REQ[4]#
6 H_A#[31 17] HIT# G6 H_HIT# 6 6 H_D#[31 16] H_D#[63 48] 6
H A#17 Y2 E4 H D#16 N22 AC22 H_D#48
A[17]# HITM# H_HITM# 6 D[16]# D[48]# H_D#49
H A#18 U5 H D#17 K25 AC23
H_A#19 A[18]# H_D#18 D[17]# D[49]# H_D#50
R3 A[19]# BPM[0]# AD4 P26 D[18]# D[50]# AB22
ADDR GROUP 1
H A#20 W6 AD3 H D#19 R23 AA21 H D#51
A[20]# BPM[1]# D[19]# D[51]#
XDP/ITP SIGNALS
H A#21 U4 AD1 H D#20 L25 AB21 H_D#52
A[21]# BPM[2]# D[20]# D[52]#
DATA GRP 1
DATA GRP 3
H_A#22 Y5 AC4 H_D#21 L22 AC25 H_D#53
H A#23 A[22]# BPM[3]# TPC28T 1 T1 +VCCP_AGTL+ H D#22 D[21]# D[53]# H D#54
C
H A#24
U2
R4
A[23]# PRDY# AC2
AC1 H_PREQ# AGTL+ I/O H D#23
L23
M23
D[22]# D[54]# AD20
AE22 H_D#55 C
A[24]# PREQ# D[23]# D[55]#
H_A#25 T5 A[25]# TCK AC5 H_TCK
CPU Voltage H_D#24 P25 D[24]# D[56]# AF23 H_D#56
1
H_A#26 T3 AA6 H_TDI H_D#25 P22 AD24 H_D#57
H A#27 W3
A[26]# TDI
AB3 H_TDO Debug R2 Reference H D#26 P23
D[25]# D[57]#
AE21 H_D#58
H_A#28 A[27]# TDO H_TMS H_D#27 D[26]# D[58]# H_D#59
W5 AB5 T24 AD21
H_A#29 Y4
A[28]# TMS
AB6 H_TRST# Port 56Ohm +VCCP_AGTL+ H_D#28 R24
D[27]# D[59]#
AE25 H_D#60
H A#30 A[29]# TRST# R3 D[28]# D[60]# H_D#61
W2 A[30]# DBR# C20 1 2 0Ohm SYS_RST# 26
H D#29 L26 D[29]# D[61]# AF25
H_A#31 / H_D#30 H_D#62
2
Y1 A[31]# T25 D[30]# D[62]# AF22
1
V4 D21 H_PROCHOT_S# H_D#31 N24 AF26 H_D#63
6 H_ADSTB#1 ADSTB[1]# PROCHOT# H_PROCHOT_S# 40 D[31]# D[63]#
A24 R4 M24 AD23
THERMDA H_THERMDA 5 6 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 6
THERM
A6 A25 1KOhm N25 AE24
24 H_A20M# A20M# THERMDC H_THERMDC 5 6 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 6
A5 1% M26 AC20
24 H_FERR# FERR# 6 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 6
24 H_IGNNE# C4 IGNNE# THERMTRIP# C7 PM_THRMTRIP# 5,7,24 (No stub)
GTL_REF H_COMP0
2
AD26 GTLREF COMP[0] R26
(No stub) MISC H_COMP1
24 H_STPCLK# D5 STPCLK# COMP[1] U26 AGTL+ I/O Buffer
1
TPC28T 1 T2 1KOhm / H_COMP2
HCLK
24 H_INTR C6 LINT0 COMP[2] U1
24 H_NMI B4 LINT1 BCLK[0] A22 CLK_CPU_BCLK 28
R5 R6 2 1 test1 C26 TEST1 COMP[3] V1 H_COMP3 Compensation
A3 A21 2KOhm
24 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 28 test2
1 1% R7 2 1 D25 E5
TEST2 DPRSTP# H_DPRSTP# 24,50
AA1 TPC28T T3 B5
RSVD[1] DPSLP# H_DPSLP# 24
51Ohm
2
AA4 RSVD[2] RSVD[12] T22 DPWR# D24 H_DPWR# 6
AB2 A2 CPU BSEL0 B22 D6 H PWRGD
RSVD[3] RSVD[A2] 28 CPU_BSEL0 CPU_BSEL1 BSEL[0] PWRGOOD H_PWRGD 24
AA3 RSVD[4] 28 CPU_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 6,24
CPU_BSEL2
RESERVED
M4
N5
RSVD[5] RSVD[13] D2
F6
Default Strapping When Not Used 28 CPU_BSEL2 C21 BSEL[2] PSI# AE6 PM_PSI# 50
RSVD[6] RSVD[14]
T2 RSVD[7] RSVD[15] D3 BCLK FSB BSEL2BSEL1BSEL0 SOCKET479P
V3 C1 +VCCP_AGTL+
RSVD[8] RSVD[16]
B2 RSVD[9] RSVD[17] AF1
H_PREQ#
133 533 L L H
C3 D22 R8 2 1 54.9Ohm 1%
RSVD[10] RSVD[18] H_TDI R9 54.9Ohm 1%
RSVD[19] C23
H_TDO
2 1 166 667 L H H AGTL+ I/O Buffer Compensation
B B25 C24 R10 2 1 54.9Ohm / 1% B
RSVD[11] RSVD[20] H_TMS R11 54.9Ohm 1%
2 1
SOCKET479P
H_TCK
Length <= 0.5" Length <= 0.5"
R12 2 1 54.9Ohm 1%
H_TRST# R13 1 2 680Ohm / JP8 / Zo=27.4 ohm Zo=27.4 ohm
test1 1 1 2 2 test2 Space>= 20 mils Space>= 20 mils
SGL_JUMP
R14 R15
27.4Ohm 27.4Ohm
H_COMP0 1 2 H_COMP2 1 2
1% 1%
Length <= 0.5" Length <= 0.5"
Zo=55 ohm Zo=55 ohm
Space>= 20 mils Space>= 20 mils
R16 R17
54.9Ohm 54.9Ohm
H_COMP1 1 2 H_COMP3 1 2
1% 1%
A A
Title : CPU-YONAH(HOST)
ASUSTeK COMPUTER INC. NB1 Engineer Mark , Frank
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