Service Manuals, User Guides, Schematic Diagrams or docs for : asus ASUS_A3N
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5 4 3 2 1
FILE LIST 01
01_BLOCK DIAGRAM
02_POWER DIAGRAM
THERMAL
A3
03_CPU-BANIAS(HOST)
04_CPU-BANIAS(PWR)
05
05_THERMAL
D POWER 06_NB-MCHM(DDR) D
BLOCK BANIAS 37 38 39
(IMVP4)
40 41 42 43 44 45
07_NB-MCHM(HOST)
08_NB-MCHM(VGA)
09_NB-MCHM(PWR)
FAN
DIAGRAM 35 03
24.5W
04
10_DUAL DDR SODIMM
11_DDR TERMINATION
12_LVDS & BACKLIGHT
13_CRT CONNECTOR
PSB 14_ICH4-M(HUB_PCI)
15_ICH4-M(H_U_IDE_PM)
DDR TERMINATION 16_ICH4-M(PWR)
North LVDS MCHM 17_ICH4-M_PULLUP
Bridge DDR CPU LCD 11 855GM/GME:266/333 18_CLOCK-ICS950815
Celeron/ Banias/ MONTARA
A3N 855GM 266 Dothan(400) 852GM/GMV/GME:266/266/333 19_LAN-RTL8100CL
12
Celeron/ Banias/ -GM 20_MINIPCI
A3L 852GM 266 Dothan(400) DDR
C
RGB 21_CB1394-R5C593(1) C
Celeron/ Banias/ 3.8W DUAL DDR SODIMM
A3Ne/A6Ne 855GME 333 Dothan(400) CRT 22_CB1394-R5C593(2)
Celeron/ Banias/ 23_PCMCIA SOCKET
852GME 333 Dothan(400)/ Dothan(533) 13 10 24_IDE-HD
Celeron/ Banias/ 06 07 08 09
A3Le 852GMV 266 Dothan(400)/ Dothan(533) 25_IDE-ODD
HUB 26_KBC-M38857
AC97 SECONDARY IDE 27_SIO-ITE7805
AUDIO AMP AC'97 28_IR&LPT_PORT
CLOCK CODEC ICH4 IDE 25
& MIC 29_DISCHARGE CIRCUIT
GEN Ultra 30_CODEC-ALC650
30 2.9W
31 32 ATA100 31_AUDIO AMP
PRIMARY IDE 32_MIC
18
MDC 33_MDC&RJ45&RJ11
24
34_USB
33 35_FAN&Audio DJ
B
36_FUNCTION KEY B
PCI LPC 37_PWR & RESET SEQ
38_VCORE
14 15 16 17 39_1.25V&1.8V
40_2.5V&1.5V&1.35V&1.05V
1394 41_SYSTEM
1394 MINIPCI LAN 42_LOAD SWITCH
CARDBUS USB 2.0 KBC SIO 43_CHARGER
Card & SIR 44_PIC16C54
Reader 21 22 DEBUG 19 45_BATLOW/SD#
PORT USB X4 28 46_SCREW HOLE & M/B SETTING
22 26 27
47_REVISION(1)
PCMCIA 55_Power Net Reference
20 LAN & 48_REVISION(2)
34
Modem PRINTER 49_REVISION(3)
23
PORT 50_REVISION(4)
Jack USB X2 51_BLOCK DIAGRAM 5E
A A
for 28 SSID/SVID 52_BLOCK DIAGRAM 7H
33
CCD & LAN:1045/1043 53_Part Reference 1
Discharge Function Screw MDC:1826/1043 54_Part Reference 2
WLAN
circuit Key Hole CardBUS:1894/1043 Title : BLOCK DIAGRAM
12 1394:1897/1043 Engineer: John Hung
ASUSTek COMPUTER INC. NB1
Size Project Name Rev
29 36 46 Custom A3N/A3L 2.4
Date: Monday, November 15, 2004 Sheet 1 of 55
5 4 3 2 1
5 4 3 2 1
System work voltage +V1.25S : JP4,5 page 39
+V2.5 : JP6 page 40
Adapter in : 19.5 ~18.5 V +V1.2S : JP7 page 40
Battery in : 16.8 ~ 11.6V VR_VID0-VR_VID5 +VCCP : JP9 page 40
PM_STPCPU#.,PM_DPRSLPVR.,PCI#.,MCH_OK.,CLK_EN# +V5S : JP13 page 42
CPU_VRON +V5 : JP14 page 42
+VCORE (25A) +V1.5SUS : JP15 page 39
D
+V1.8 : JP16,19 page 39 D
AC_BAT_SYS
MAX1987 +V1.8S : JP17 page42
VRM_PWRGD
+V12 : JP18 page 42
+V1.5S : JP22 page 40
SUSC#. (3V_ON) +V5A : JP24 page 40
+5VO (5A) SUSB# +V5S
+V3.3A : JP26 or 27 page 39
LTC3728 SUSB# +V3S
+V3.3SUS (5A) +V3.3S : JP28 page 42
(Regulator) +V5
+V3.3 : JP29 page 42
+12VO (0.15A) SUSC# +V3
78L12
SUSB# +V12S
+V12
+1.5VO (2A) +V1.5S
SUSB#
+2.5VO (5A) +V2.5 SUSB# +V1.5S
SUSC#
TPS5130
+5VAO +1.2VO (2A) +V1.2S
C SUSB# C
A/D_VIN SHUT_DOWN#
SWITCH
Power
+1.05VO (1A) +VCCP
SUSB# BAT_S Signal BAT_IN#_OC
Circuit
SUSB# TS# ACIN_OC
+V2.5 CM8562 +V1.25S (2A) AC_APR_UC
(Regulator)
SUSC#
+2.5VO MIC37101-1.8 +1.8VO (1A) +V1.8
LDO
SUSB# +V1.8S
TS#
SUSB# CHG EN#
PIC + TL494 BAT AC_APR_UC PIC16C54C CHG LED_UP
(Charge) SMC_BAT PWR LED_UP
B B
SMD_BAT BAT_LLOW
FDS6679
+5VO (20mA)
A/D_VIN 78L05 SWITCH
FD6JK3TP +5VLCM
(Regulator) +5VCHG (100mA) (F02JK2E)
MIC5223MB +3VALWAYS_M +V3.3A LM4040BIM +2.5VREF
(Regulator) (Regulator) (500uA)
+V3.3SUS CM2855 +V1.5SUS
A
(LDO) A
+5VAO +5VALWAYS
Title : POWER DIAGRAM
ASUSTek COMPUTER INC. NB1 Engineer: Adams Lin
Size Project Name Rev
Custom A3N/A3L 2.4
Date: Monday, November 15, 2004 Sheet 2 of 55
5 4 3 2 1
5 4 3 2 1
CPU Pin A1 need to be enlarged(M) H_D#[63:0] 7
U31B U31A
7 H_A#[16:3]
H_A#16 AA2 N2 COMMON CLOCK -> L6 H_D#15 C25 Y25 H_D#47
A[16]# ADS# H_ADS# 7 D[15]# D[47]#
H_A#15 Y3 A10 H_PRDY# H_D#14 E23 AA26 H_D#46
H_A#14 A[15]# PRDY# H_PREQ# WIDTH: 5 mils H_D#13 D[14]# D[46]# H_D#45
H_A#13
AA3
U1
A[14]# PREQ# B10
SPACE >= 1:2 H_D#12
B23
C26
D[13]# D[45]# Y23
V26 H_D#44 DATA GROUP 0,2 -> L6
A[13]# D[12]# D[44]#
H_A#12
H_A#11
Y1 A[12]# BNR# L1 H_BNR# 7 GROUP SPACE >=1:5 H_D#11
H_D#10
E24 D[11]# D[43]# U25 H_D#43
H_D#42
DATA GROUP 1,3 -> L6
Y4 J3 H_BPRI# 7 D24 V24
ADDRESS GROUP 0
A[11]# BPRI# LENGTH: 1" - 6.5"(OPT: 4"+/-0.5") D[10]# D[42]#
SPACE >= 1:3
DATA GROUP 0
H_A#10 H_D#9 H_D#41
2
W2 A[10]# B24 D[9]# D[41]# U26
H_A#9 T4 Breakout Length:<=200 mil H_D#8 C20 AA23 H_D#40
GROUP SPACE >=1:5
DATA GROUP
H_A#8 A[9]# T107TPC28b H_D#7 D[8]# D[40]# H_D#39
D W1 A[8]# DBR# A7 1 (#0011) B20 D[7]# D[39]# R23 D
H_A#7 H_D#6 H_D#38
H_A#6
V2
R3
A[7]# H_D#5
A21
B26
D[6]# D[38]# R26
R24 H_D#37 LENGTH: 0.5" - 5.5"
A[6]# D[5]# D[37]#
H_A#5
H_A#4
V3 A[5]#
H_D#4
H_D#3
A24 D[4]# D[36]# V23 H_D#36
H_D#35
(#0012)
U4 A[4]# DEFER# L4 H_DEFER# 7 B21 D[3]# D[35]# U23
H_A#3 P4 H2 H_D#2 A22 T25 H_D#34
A[3]# DRDY# H_DRDY# 7 D[2]# D[34]#
U3 M2 H_D#1 A25 AA24 H_D#33
7 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 7 D[1]# D[33]#
H_REQ#4 T1 H_D#0 A19 Y26 H_D#32
H_REQ#3 REQ[4]# D[0]# D[32]#
P1 REQ[3]# 7 H_DINV#0 D25 DINV[0]# DINV[2]# T24 H_DINV#2 7
H_REQ#2 T2 C23 W25
REQ[2]# 7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7
H_REQ#1 P3 C22 W24
REQ[1]# 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
H_REQ#0 R2 REQ[0]# H_BR0# H_D#31 H_D#63
7 H_REQ#[4:0] N4 H_BR0# 7 K25 AF26
CONTROL
BR0# +VCCP H_D#30 D[31]# D[63]# H_D#62
N25 D[30]# D[62]# AF22
H_D#29 H26 AF25 H_D#61
H_IERR# H_D#28 D[29]# D[61]# H_D#60
IERR# A4 2 1 M25 D[28]# D[60]# AD21
0.5"-12" R271 56Ohm H_D#27 N24 AE21 H_D#59
7 H_A#[31:17] D[27]# D[59]#
H_A#31 AF1 H_D#26 L26 AF20 H_D#58
3
A[31]# D[26]# D[58]#
DATA GROUP 1
H_A#30 AE1 B5 <=10" H_D#25 J25 AD24 H_D#57
A[30]# INIT# H_INIT# 15,27 D[25]# D[57]#
H_A#29 H_D#24 H_D#56
DATA GROUP
AF3 A[29]# M23 D[24]# D[56]# AF23
ADDR GROUP 0 -> L6 H_A#28 AD6 H_D#23 J23 AE22 H_D#55
ADDRESS GROUP 1
H_A#27 A[28]# H_D#22 D[23]# D[55]# H_D#54
ADDR GROUP 1 -> L6 AE2 A[27]# LOCK# J2 <=10" H_LOCK# 7 G24 D[22]# D[54]# AD23
H_A#26 AD5 H_D#21 F25 AC25 H_D#53
SPACE >= 1:2 H_A#25 A[26]# H_D#20 D[21]# D[53]# H_D#52
AC6 A[25]# H24 D[20]# D[52]# AC22
STROBE SPACE >=1:3 H_A#24 AB4 H_D#19 M26 AC20 H_D#51
H_A#23 A[24]# H_D#18 D[19]# D[51]# H_D#50
AD2 L23 AB24
GROUP SPACE >=1:5 H_A#22 AE4
A[23]# H_D#17 G25
D[18]# D[50]#
AC23 H_D#49
H_A#21 A[22]# H_D#16 D[17]# D[49]# H_D#48
LENGTH: 0.5" - 6.5" AD3 A[21]# RESET# B11 <=3" H_CPURST# 7 H23 D[16]# D[48]# AB25
H_A#20 AC3 L2 H_RS#2 J26 AD20
A[20]# RS[2]# 7 H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 7
(#0012) H_A#19
H_A#18
AC7 A[19]# RS[1]# K1 H_RS#1
H_RS#0
7 H_DSTBN#1 K24 DSTBN[1]# DSTBN[3]# AE24 H_DSTBN#3 7
C
AC4 A[18]# RS[0]# H1 7 H_DSTBP#1 L24 DSTBP[1]# DSTBP[3]# AE25 H_DSTBP#3 7 C
H_A#17 AF4 A[17]# H_RS#[2:0] 7
AE5 M3 SOCKET479P
7 H_ADSTB#1 ADSTB[1]# TRDY# H_TRDY# 7
HIT# K3 H_HIT# 7
8 H_DPWR# 1"-6.5" C19 DPWR# HITM# K4 H_HITM# 7
+VCCP +VCCP
SOCKET479P TOPOLOGY 2A: TOPOLOGY 1B:
R-CPU-ICH Y-FORK CPU-ICH-R
1
1
H_VID5
H_VID4 VR_VID5 38
VR_VID4 38
CPU-ICH: 0.5" - 12" CPU-ICH: 0.5" - 12" +VCCP
H_VID3 R73 R71
T92 TPC28b _CLK_CPU_BCLK H_VID2 VR_VID3 38 R - CPU <= 3"
332Ohm
ICH-R <= 3"
56Ohm
Close to
1 VR_VID2 38 (#0013) (#0013)
1
T95 TPC28b 1_CLK_CPU_BCLK# H_VID1
VR_VID1 38
Pin AD26
H_VID0 H_PWRGD H_FERR#
2
2
VR_VID0 38
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