Service Manuals, User Guides, Schematic Diagrams or docs for : asus ASUS_Z62HA NB SIS672 SB SIS968
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5 4 3 2 1
CPU ITP CONN.
MEROM
Socket-P CLOCK GEN
Z62Ha
ICS 9LPR600C
D D
DDR2 32MX16M X4
DDR CLOCK
BUFFER THERMAL SENSOR
ICS 9P935AF MAX6657MSA
ATI GPU M72-S
LCD NORTH
DDR2 single
632 BGA BRIDGE Channel-1 DDR2 SO-DIMM1
CRT
DDR2 667MHz/533MHz
SIS672
DDR2 single
Channel-2
DDR2 SO-DIMM2
DDR2 667MHz/533MHz
Debug
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MUTIOL 133MHz
Internal KB Connector
CBB AUDIO AMP.
SATA HDD TI TPA6017A2
C
TPM 1.2 C
Touch Pad INFINEON SLB9635 SOUTH MIC AMP. INT. MIC
ODD
Synaptics
BRIDGE
MIC-IN JACK
EC SPI EC SIS968
FLASH ENE3925
AZALIA CODEC Head-Phone JACK
Realtek ALC883
BIOS - SPI FLASH
MDC CONN. 2PIN CONN.
Card Reader RJ11
B 3 in 1 Card 1394 Ricoh B
Reader R5C833
Digitally signed by dd
DN: cn=dd, o=dd,
ou=dd,
email=dddd@yahoo. RJ45 GIGA LAN
RTL8110SCL
com, c=US
MINICARD Slot
Date: 2009.11.28 for WLAN
07:26:12 +07'00' USB Port X2
USB Port X2 NEWCARD
Bluetooth CONN.
A A
CMOS Camera
888
0.3M Pixels
Title : Block Diagram
ASUSTek Computer INC. Engineer: Jack Hsu
Size Project Name Rev
Custom Z62Ha 1.1
Date: Thursday, September 27, 2007 Sheet 1 of 70
5 4 3 2 1
5 4 3 2 1
EC GPIO SETTING Pin Pin Name Signal Name Type
48 GPH0 VSUS_ON O
Pin Pin Name Signal Name Type 54 GPH1 VSUS_GD# I
32 PWM0/GPA0 BL_PWM_DA O
55 GPH2 CPUPWR_GD# I
33 PWM1/GPA1 FAN_PWM O
69 GPH3 PM_PWRBTN# O PCI Device IDSEL# REQ/GNT# Interrupts
36 PWM2/GPA2 CLK_PWRSAVE# O
70 GPH4 SUSC_ON O
37 PWM3/GPA3 /
75 GPH5 SUSB_ON O CARD READER AD22 0 INTB-->INTB
38 PWM4/GPA4 CHG_LED_UP# O
76 GPH6 CPU_VRON O 1394 AD22 0 INTA-->INTA
D 39 PWM5/GPA5 PWR_LED_UP# O D
105 GPH7 PM_RSMRST# O LAN AD24 REQ#2/GNT#2 INTA-->INTC
40 PWM6/GPA6 /
148 GPI0 ICH7_PWROK O
43 PWM7/GPA7 LCD_BACKOFF# O
149 GPI1 /
153 RXD/GPB0 NUM_LED O
152 GPI2 MCHOK I
154 TXD/GPB1 CAP_LED O SM-Bus Device SM-Bus Address
155 GPI3 CHG_EN# O
162 GPB2 SCRL_LED O Clock Generator 1101001x ( D2 )
156 GPI4 PRECHG O
163 SMCLK0/GPB3 SMB0_CLK I/0 SO-DIMM 0 1010000x ( A0 )
168 GPI5 BAT_LL# O
164 SMDAT0GPB4 SMB0_DAT I/0 SO-DIMM 1 1010001x ( A2 )
174 GPI6 BAT_LEARN O
5 GA20/GPB5 A20GATE O Thermal Sensor 0101110x ( 5C )
6 KBRST#/GPB6 RC_IN# O
ICH7-M GPIO SETTING
165 GPB7 /
47 CLKOUT/GPC0 /
Pin Pin Name Signal Name Type Power_Well Default
AB18 GPIO00/BM_BUSY# PM_BMBUSY# I Core(To:3.3V) GPI
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169 SMCLK1/GPC1 SMB1_CLK I/0
C8 GPIO01/REQ5# PCI_REQ#5 I/O Core(To:5V) GPI
170 SMDAT1/GPC2 SMB1_DAT I/0
G8 GPIO02/PIRQE# PCI_INTE# I(OD) Core(To:5V) GPI
171 GPC3 Mail_LED O
F7 GPIO03/PIRQF# PCI_INTF# I(OD) Core(To:5V) GPI
C 172 TMRI0/WUI2/GPC4 AC_OK# I C
F8 GPIO04/PIRQG# PCI_INTG# I(OD) Core(To:5V) GPI
175 GPC5 OP_SD# O
G7 GPIO05/PIRQH# PCI_INTH# I(OD) Core(To:5V) GPI
176 TMRI1/WUI3/GPC6 BAT_IN_OC# I
AC21 GPIO06 NC I/O Core(To:3.3V) GPI
1 CK32KOUT/GPC7 /
AC18 GPIO07 WLAN_BT_LED_EN# I Core(To:3.3V) GPI
26 RI1#/WUI0/GPD0 SUSB# I
E21 GPIO08 EXTSMI# I SUS(To:3.3V) GPI
29 RI2#/WUI1/GPD1 SUSC# I
E20 GPIO09 SATA_DET#0 I/O SUS(To:3.3V) GPI
30 LPCRST#/WUI4//GPD2 PLT_RST# I
A20 GPIO10 WLAN_ON# O SUS(To:3.3V) GPI
31 ECSCI#/GPD3 EXT_SCI# O
B23 SMBALERT#/GPIO11 SMB_ALERT# I/O SUS(To:3.3V) Native
41 GPD4 /
F19 GPIO12 KBC_SCI# I SUS(To:3.3V) GPI
42 GINT/GPD5 /
E19 GPIO13 TP I/O SUS(To:3.3V) GPI
62 TACH0/GPD6 FAN0_TACH I
R4 GPIO14 NC I/O SUS(To:3.3V) GPI
63 TACH1/GPD7 /
E22 GPIO15 CB_SD# I/O SUS(To:3.3V) GPI
87 ADC4/GPE0 EMAIL_SW# I
AC22 GPIO16 PM_DPRSLPVR O Core(To:3.3V) Native
88 ADC5/GPE1 INTERNET# I
D8 GPIO17/GNT5# PCI_GNT#5 I/O Core(To:3.3V) GPO
89 ADC6/GPE2 PWR4G_SW# I
AC20 GPIO18/STP_PCI# STP_PCI# O Core(To:3.3V) GPO
90 ADC7/GPE3 DISTP_SW# I
B AH18 GPIO19/SATA1GP NC O Core(To:3.3V) GPI B
2 PWRSW/GPE4 PWR_SW# I
AF21 GPIO20/STP_CPU# STP_CPU# O Core(To:3.3V) GPO
44 WUI5/GPE5 /
AE19 GPIO21/SATA0GP NC I/O Core(To:3.3V) GPI
24 LPCPD#/WUI6/GPE6 LID_EC# I
A13 GPIO22/REQ4# PCI_REQ#4 I/O Core(To:3.3V) Native
25 CLKRUN#/WUI7/GPE7 /
AA5 LDRQ1#/GPIO23 TP I/O Core(To:3.3V) Native
110 PS2CLK0/GPF0 /
R3 GPIO24 NC I/O SUS(To:3.3V) GPO
111 PS2DAT0/GPF1 /
D20 GPIO25 NC I/O SUS(To:3.3V) GPO
114 PS2CLK1/GPF2 / I
A21 GPIO26/EL_RSVD NC I/O SUS(To:3.3V) GPO
115 PS2DAT1/GPF3 / I
B21 GPIO27/EL_STATE0 PD_DET# I/O SUS(To:3.3V) GPO
116 PS2CLK2/GPF4 TP_CLK I/0
E23 GPIO28/EL_STATE1 NC I/O SUS(To:3.3V) GPO
117 PS2DAT2/GPF5 TP_DAT I/0
C3 GPIO29/OC#5 USB_OC#5 I/O SUS(To:3.3V) Native
118 PS2CLK3/GPF6 /
A2 GPIO30/OC#6 NEWCARD_OC# I SUS(To:3.3V) Native
119 PS2DAT3/GPF7 /
B3 GPIO31/OC#7 USB_OC#7 I/O SUS(To:3.3V) Native
113 FA16/GPG0 FA16 O
AG18 GPIO32/CLKRUN# PM_CLKRUN# O Core(To:3.3V) GPO
112 FA17/GPG1 FA17 O
AC19 GPIO33/AZ_DOCK_EN# BT_ON# O Core(To:3.3V) GPO
104 FA18/GPG2 FA18 O
A U2 GPIO34/AZ_DOCK_RST# NC I/O Core(To:3.3V) GPO A
103 FA19/GPG3 /
AD21 GPIO35 NC I/O Core(To:3.3V) GPO
3 FA20/GPG4 THRM_CPU# I
AH19 GPIO36/SATA2GP NC I/O Core(To:3.3V) GPI
4 FA21/GPG5 / 888
AE19 GPIO37/SATA3GP PCB_ID0 I Core(To:3.3V) GPI
27 LPC80HL/GPG6 PMTHERM# O
28 LPC80LL/GPG7 AC_APR_UC# I
AD20 GPIO38 PCB_ID1 I Core(To:3.3V) GPI Title : System Setting
AE20 GPIO39 PCB_ID2 I Core(To:3.3V) GPI ASUSTek Computer INC. Engineer: Jack Hsu
A14 GNT4#/GPIO48 PCI_GNT#4 I/O Core(To:3.3V) Native Size Project Name Rev
AG24 GPIO49/CPUPWRGD H_PWRGD I V_CPU_IO Native
Custom Z62Ha 1.1
Date: Thursday, September 27, 2007 Sheet 2 of 70
5 4 3 2 1
5 4 3 2 1
+VCCP_CPU
U1A U1B
<6> H_A#[16:3] H_A#3 H_BREQ0# <6> H_D#[15:0] H_D#0 H_D#32 H_D#[47:32] <6>
J4 H1 HR26 1 2 1%
Do Not Stuff /X E22 Y22
A[3]# ADS# H_ADS# <6> D[0]# D[32]#
0
ADDR GROUP
H_A#4 L5 E2 H_IERR# HR1 1 2 56Ohm 1% H_D#1 F24 AB24 H_D#33
H_A#5 A[4]# BNR# H_BNR# <6> H_PROCHOT# H_D#2 D[1]# D[33]# H_D#34
L4 G5 HR2 1 2 1%
Do Not Stuff /X E26 V24
H_A#6 A[5]# BPRI# H_BPRI# <6> H_CPURST# H_D#3 D[2]# D[34]# H_D#35
K5 HR38 1 2 Do Not Stuff
1% /X G22 V26
A[6]# D[3]# D[35]#
DATA GRP 0
H_A#7 M3 H5 H_PWRGD HR12 1 2 Do Not Stuff
1% /X H_D#4 F23 V23 H_D#36
H_A#8 A[7]# DEFER# H_DEFER# <6> H_DPSLP# H_D#5 D[4]# D[36]# H_D#37
N2 F21 HR39 1 2 56Ohm 1% G25 T22
H_A#9 A[8]# DRDY# H_DRDY# <6> H_D#6 D[5]# D[37]# H_D#38
J1 A[9]# DBSY# E1 H_DBSY# <6> E25 D[6]# D[38]# U25
H_A#10 N3 H_D#7 E23 U23 H_D#39
H_A#11 A[10]# H_BREQ0# H_D#8 D[7]# D[39]# H_D#40
P5 A[11]# BR0# F1 H_BREQ0# <6> K24 D[8]# D[40]# Y25
H_A#12 CPU_TEST1 H_D#9 H_D#41
DATA GRP 2
P2 HR7 1 2 Do Not Stuff /X
1% G24 W22
A[12]# D[9]# D[41]#
CONTROL
D H_A#13 L2 D20 H_IERR# HR10 1 1%
2 Do Not Stuff /X CPU_TEST2 H_D#10 J24 Y23 H_D#42 D
H_A#14 A[13]# IERR# GND CPU_TEST4 H_D#11 D[10]# D[42]# H_D#43
P4 B3 HC10 1 2 Do Not Stuff /X J23 W24
H_A#15 A[14]# INIT# H_INIT# <14> H_D#12 D[11]# D[43]# H_D#44
P1 A[15]# H22 D[12]# D[44]# W25
H_A#16 R1 H4 H_D#13 F26 AA23 H_D#45
A[16]# LOCK# H_LOCK# <6> H_D#14 D[13]# D[45]# H_D#46
<6> H_ADSTB#0 M1 ADSTB[0]# K22 D[14]# D[46]# AA24
C1 H_CPURST# H_D#15 H23 AB25 H_D#47
<6> H_REQ#[4:0] H_REQ#0 RESET# H_CPURST# <6> D[15]# D[47]#
K3 REQ[0]# RS[0]# F3 H_RS#0 <6> <6> H_DSTBN#0 J26 DSTBN[0]# DSTBN[2]# Y26 H_DSTBN#2 <6>
H_REQ#1 H2 F4 H26 AA26
H_REQ#2 REQ[1]# RS[1]# H_RS#1 <6> <6> H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 <6>
K2 REQ[2]# RS[2]# G3 H_RS#2 <6> <6> H_DINV#0 H25 DINV[0]# DINV[2]# U22 H_DINV#2 <6>
H_REQ#3 J3 G2
H_REQ#4 REQ[3]# TRDY# H_TRDY# <6>
L1 REQ[4]# <6> H_D#[31:16] H_D#[63:48] <6>
G6 H_D#16 N22 AE24 H_D#48
<6> H_A#[35:17] H_A#17 HIT# H_HIT# <6> H_D#17 D[16]# D[48]# H_D#49
Y2 A[17]# HITM# E4 H_HITM# <6> K25 D[17]# D[49]# AD24
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# XDP_BPM#0 H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
1
ADDR GROUP
H_A#20 W6 AD3 XDP_BPM#1 H_D#20 L23 AB21 H_D#52
A[20]# BPM[1]# D[20]# D[52]#
DATA GRP 1
H_A#21 U4 AD1 XDP_BPM#2 H_D#21 M24 AC26 H_D#53
H_A#22 A[21]# BPM[2]# XDP_BPM#3 H_D#22 D[21]# D[53]# H_D#54
XDP/ITP SIGNALS
Y5 A[22]# BPM[3]# AC4 L22 D[22]# D[54]# AD20
H_A#23 U1 AC2 XDP_BPM#4 H_D#23 M23 AE22 H_D#55
H_A#24 A[23]# PRDY# XDP_BPM#5 H_D#24 D[23]# D[55]# H_D#56
R4 A[24]# PREQ# AC1 P25 D[24]# D[56]# AF23
H_A#25 T5 AC5 XDP_TCK H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK XDP_TDI H_D#26 D[25]# D[57]# H_D#58
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21
+VCCP_CPU
DATA GRP 3
H_A#27 W2 AB3 XDP_TDO H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO XDP_TMS H_D#28 D[27]# D[59]# H_D#60
W5 AB5 R24 AC22
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H_A#29 A[28]# TMS XDP_TRST# Zo=55 ohm, 0.5" max H_D#29 D[28]# D[60]# H_D#61
Y4 A[29]# TRST# AB6 L25 D[29]# D[61]# AD23
2
H_A#30 U2 C20 XDP_DBR# for GTLREF H_D#30 T25 AF22 H_D#62
H_A#31 A[30]# DBR# HR3 H_D#31 D[30]# D[62]# H_D#63
V4 A[31]# N25 D[31]# D[63]# AC23
H_A#32 W3 1KOhm L26 AE25
H_A#33 A[32]# <6> H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 <6>
AA4 THERMAL 1% M26 AF24
H_A#34 A[33]# <6> H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 <6>
AB2 HR37 1 2 0Ohm N24 AC20
H_A#35 A[34]# H_PROCHOT#_SB <14> <6> H_DINV#1 DINV[1]# DINV[3]# H_DINV#3 <6>
D21 H_PROCHOT#
1
C
AA3 A[35]# PROCHOT# C
<6> H_ADSTB#1 V1 ADSTB[1]# THRMDA A24 H_THERMDA CPU_GTLREF AD26 GTLREF COMP[0] R26 H_COMP0 HR4 1 2 27.4Ohm 1%
THRMDC B25 H_THERMDC CPU_TEST1 C23 TEST1 MISC COMP[1] U26 H_COMP1 HR5 1 2 54.9Ohm 1%
A6 CPU_TEST2 D25 AA1 H_COMP2 HR6 1 2 27.4Ohm 1%
<14> H_A20M# A20M# TEST2 COMP[2]
2
ICH
A5 C7 T110 CPU_TEST3
1 Do Not Stuff C24 Y1 H_COMP3 HR8 1 2 54.9Ohm 1%
<14> H_FERR# FERR# THERMTRIP# PM_THRMTRIP# <14> TEST3 COMP[3] GND
3
2
C4 3 HQ1 HR9 HC9 CPU_TEST4 AF26
<14> H_IGNNE# IGNNE# D TEST4
H2N7002 2KOhm 0.1UF/16V T111 CPU_TEST5
1 Do Not Stuff AF1 E5 H_DPRSTP#
CPU_TEST6 TEST5 DPRSTP# H_DPSLP# H_DPRSTP# <14,27,56>
D5 1% T112 1 Do Not Stuff A26 B5
<14> H_STPCLK# STPCLK# 11 TEST6 DPSLP# H_DPWR# H_DPSLP# <27>
H CLK
1
<14> H_INTR C6 LINT0 THRO_CPU <24> DPWR# D24 H_DPWR# <6>
B4 A22 G 1
B22 D6 H_PWRGD
<14> H_NMI LINT1 BCLK[0] CLK_CPU_BCLK <23> S 2 <23> CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGD <6>
<14> H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# <23> <23> CPU_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# <14>
2
<23> CPU_BSEL2 C21 BSEL[2] PSI# AE6 PM_PSI# <56>
T100 1 CPU_RSVD1
Do Not Stuff M4 GND GND
T101 CPU_RSVD2
Do Not Stuff RSVD1 SOCKET478B
1 N5 RSVD2
T102 CPU_RSVD3
Do Not Stuff
T103
1
1 CPU_RSVD4
Do Not Stuff
T2
V3
RSVD3 GND
GTLREF = 2/3*Vccp +-2% Comp0,2 connect with Zo=27.4ohm, make
T104 CPU_RSVD5
Do Not Stuff RSVD4
RESERVED
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