Service Manuals, User Guides, Schematic Diagrams or docs for : asus ASUS K70IJ Rev1.0
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5 4 3 2 1
01 Block Diagram 61 *
02 System Setting 62 USB CONN CPU CLOCK GEN
03
04
POWER SEQUENCE
CPU-Penryn(HOST)
63
64
*
* Penryn
35W
ICS9LPR363DGLF-T K70IJ
05 CPU-Penryn(PWR) 65 * PAGE 39
06 * 66 * PAGE 4,5
07 Cantiga(HOST) 67 DEBUG CONN zHM008:BSF
zHM008:BSF
zHM008:BSF
zHM008:BSF THERMAL CONTROL
D 08 Cantiga(DMI & CFG) 68 DC & BAT IN PAGE 38 D
09 Cantiga(GRAPHIC) 69 *
10 Cantiga(DDR2) 70 *
11 Cantiga(PWR) 71 * LCD
12 Cantiga(PWR2) 72 SATA-HDD & ODD PAGE 33 NORTH zHM008:2RDD
zHM008:2RDD
zHM008:2RDD
zHM008:2RDD DDR2 SO-DIMM0_On-Board 2G
13 Cantiga(GND) 73 *
CRT
BRIDGE PAGE 23,24
14 * 74 HOLE & Spring
15 SB-ICH9M(1)_SATA 75 * PAGE 32 Cantiga GL40 zHM008:2RDD
zHM008:2RDD
zHM008:2RDD
zHM008:2RDD
16 SB-ICH9M(2)_PCIE/USB 76 EXPRESS GATE
DDR2 SO-DIMM1 Socket PAGE 21
17 SB-ICH9M(3)_PM/GPIO 77 History
18 SB-ICH9M(PWR) 78 * PAGE 7,8,9,10,11,12,13
DDR2 PAGE 21,22,23,24,25
19 * 79 *
20 DDR2 SO-DIMM0 80 POWER_VCORE IMD 4x
IMD 4x
IMD 4x
IMD 4x
21 DDR2 SO-DIMM1 81 POWER_SYSTEM
22 DDR2 TERMINATION 82 POWER_I/O_1.5VS & 1.05VS
23 * 83 POWER_I/O_DDR & VTT
ATAS
ATAS
ATAS
ATAS
C
SATA HDD C
24 * 84 POWER_I/O(Empty)
PAGE 53
25 * 85 POWER_VGA_CORE&1.1VS(Empty)
CPL
CPL
CPL
26 * 86 POWER_MCH_CORE(Empty)
SOUTH
SATA ODD
27 * 87 POWER_CHARGER
PAGE 76 BRIDGE PAGE 72
28 * 88 POWER_DETECT
29 * 89 POWER_LOAD SWITCH SPI ROM ICH9M
30 EC_IT8512E-L(1/2) 90 POWER_PROTECT PAGE 30 EC
31 EC_IT8512E-L(2/2) 91 POWER_SIGNAL ITE IT8502E-L
32 CRT 92 POWER_FLOWCHART PAGE 30 AILAZA INT SPEAKER
33 LVDS & INVERTER CONNECTOR 93 POWER_HISTORY
PAGE 15,16,17,18
AZALIA CODEC PAGE37
34 BT VIA VT1708S
Internal KB Touch Pad EXT MIC
35 *
PAGE 31 PAGE 31 PAGE 37
36 CONEXANT CX20582
37 CONEXANT_HP/MIC
INT MIC1
38 THER SENSOR & FAN
B PAGE 33 B
39 CLOCK GEN-ICS9LPR363DGLF-T
40 * BSU
41 Switch Button & LED USB Port X4 1x EICP
1x EICP
1x EICP
1x EICP
42 DISCHARGE PAGE 34
MINICARD WLAN PAGE 46
43 * BSU
44 PCI-E LAN_RTL8111C CMOS Camera
45 MDC & RJ45+11 PAGE 33
46 Mini card_WLAN+3G
BSU
CardReader
47 *
PAGE 53
48 * 1x EICP
49 * LAN AR8121 PAGE 44,45
50 *
51 *
52 *
53 CardReader & SIM CONN & TPM
A A
54 NEWCARD
55 *
56 HDA level shifter
57 iHDMI
58 *
Title : Block Diagram
ASUSTek Computer INC. NB1 Engineer: Leon
59 *
Size Project Name Rev
60 * Custom K70IJ 1.0
Date: W ednesday, April 29, 2009 Sheet 1 of 96
5 4 3 2 1
5 4 3 2 1
ICH9-M GPIO Use As Signal Name Power EC GPIO Use As Signal Name Power EC GPIO Use As Signal Name Power PCI Device IDSEL# REQ/GNT# Interrupts
GPIO 00 GPI PM_SYNC#(programmed as GPO) +3VS GPA0 GPO PWR_LED# - - -
GPIO 01 GPI - +3VS GPA1 GPO CHG_LED# GPG6 GPO -
GPIO [2:5] GPI PCI_INT[E:H]# EXT PU +5VS GPA2 GPO - - - -
GPIO 06 GPI BIOS_REC EXT PU +3VS GPA3 - - GPH0 OD PM_CLKRUN# PCIE Device Bus PCIE Device Bus
GPIO 07 GPO SEL_VID2 - +3VS GPA4 GPO LCD_BL_PWM GPH1 ALT - WLAN PE(T/R)(p/n)2
GPIO 08 GPI EXT_SMI# EXT PU +3VSUS GPA5 GPO FAN0_PWM GPH2 ALT CHG_EN GLAN PE(T/R)(p/n)6
D D
GPIO 09 Native - +3VSUS GPA6 GPO VCORE_CNT1 GPH3 GPO -
GPIO 10 GPI RTLAN_DSM# EXT PU +3VSUS GPA7 GPO VCORE_CNT2 GPH4 GPO -
EXT_SCI#(Programmed as GPI)
SM-Bus Device SM-Bus Address
GPIO 11 Native +3VSUS GPB0 GPO BATSEL_0 GPH5 GPO NUM_LED#
Clock Generator 1101001x ( D2 )
GPIO 12 GPO GPIO12 +3VSUS GPB1 GPO BATSEL_1 GPH6 GPO CAP_LED#
-
SO-DIMM 0 1010000x ( A0 )
GPIO 13 GPI +3VSUS GPB2 GPI - - - -
SO-DIMM 1 1010001x ( A2 )
GPIO 14 GPI AC_PRESENT EXT PD +3VSUS GPB3 ALT SMB0_CLK GPI0 GPI VGA_ALERT#
CPU Thermal Sensor(MAX6619) 1001100x ( 98 )
- - - - GPB4 ALT SMB0_DAT GPI1 GPI SUS_PWRGD
GPIO 16 Native PM_DPRSLPVR INT PD* +3VS GPB5 OD A20GATE GPI2 GPI ALL_SYSTEM_PWRGD
GPIO 17 GPI WLAN_LED(Programmed as GPO) +3VS GPB6 OD RC_IN# GPI3 GPI VRM_PWRGD
GPIO 18 GPO SEL_VID3 - +3VS GPB7 GPO PM_RSMRST# GPI4 GPI RECOVERY
GPIO 19 GPO SEL_VID0 - +3VS GPC0 GPI - GPI5 GPI ADP_ERR#
GPIO 20 GPO SEL_VID4 - INT PD* +3VS GPC1 ALT SMB1_CLK GPI6 GPI -
GPIO 21 GPO VID_SW - High Active +3VS GPC2 ALT SMB1_DAT GPI7 GPI -
GPIO 22 GPI BT_DET# EXT PU +3VS GPC3 GPO PM_PWRBTN# GPJ0 GPO HDCP_EPROM_PROTECT#
GPIO 23 Native LPC_DRQ#1 INT PU +3VS GPC4 ALT AC_IN_OC# GPJ1 GPO PM_PWROK
C C
GPIO 24 GPO - +3VSUS GPC5 GPO OP_SD# GPJ2 GPI VSET_EC
- - - - GPC6 ALT TS1# GPJ3 - ISET_EC
GPIO 26 Native PM_S4_STATE# +3VSUS GPC7 GPO RFON_SW# GPJ4 GPO -
GPIO 27 GPO SEL_VID5 +3VSUS GPD0 GPI PWRLIMIT# GPJ5 GPO -
GPIO 28 GPO SEL_VID6 +3VSUS GPD1 ALT PM_SUSC#
GPIO 29 Native USB_OC#_ALL +3VSUS GPD2 ALT BUF_PLT_RST#
GPIO 30 Native CLK_DEC# +3VSUS GPD3 OD EXT_SCI#
GPIO 31 Native CLK_ACC +3VSUS GPD4 OD EXT_SMI#
- - - - GPD5 GPO LCD_BACKOFF#
GPIO 33 GPO - INT PU* +3VS GPD6 ALT FAN0_TACH
GPIO 34 GPO - +3VS GPD7 GPI -
GPIO33 Internal Pull High, Go Low= Flash
GPIO 35 GPO GPO35 +3VS GPE0 GPO VSUS_ON
Descriptor Security will be overriden
GPIO 36 GPO SEL_VID1 - +3VS GPE1 GPO SUSC_EC#
GPIO 37 GPI PCB_ID0 +3VS GPE2 GPO SUSB_EC#
GPIO 38 GPI PCB_ID1 +3VS GPE3 GPO CPU_VRON
B
GPIO 39 GPI PCB_ID2 +3VS GPE4 ALT PWR_SW# B
GPIO 40 Native USB_CON_OC01# +3VSUS GPE5 ALT BAT2_IN_OC#
GPIO 41 Native USB_CON_OC23# +3VSUS GPE6 GPI LID_SW#
GPIO 42 Native USB_CON_OC23# +3VSUS GPE7 GPO DJ_SW#
GPIO 43 Native USB_OC#_ALL +3VSUS GPF0 GPI -
GPIO 44 Native USB_OC#_ALL +3VSUS GPF1 GPI -
GPIO 45 Native USB_OC#_ALL +3VSUS GPF2 ALT MARATHON#
GPIO 46 Native WLAN_ON +3VSUS GPF3 ALT -
GPIO 47 Native USB_OC#_ALL +3VSUS GPF4 ALT TP_CLK
GPIO 48 GPI - +3VS GPF5 ALT TP_DAT
GPIO 49 GPO - +3VS GPF6 GPO THRO_CPU
GPIO 50 Native PCI_REQ1# +5VS GPF7 GPO -
GPIO 51 Native PCI_GNT1# INT PU* +3VS GPG0 GPI PM_THERM#
GPIO 52 Native PCI_REQ2# +5VS GPG1 ALT PM_SUSB#
INT PU*: PU or PD in
GPIO 53 Native PCI_GNT2# INT PU* +3VS GPG2 GPO -
A GPIO 54 Native PCI_REQ3# +5VS - - - A
GPIO 55 Native PCI_GNT3# INT PU* +3VS - - -
special time
GPIO 56 GPI - EXT PU +3VSUS
GPIO 57 GPI - EXT PU +3VSUS
GPIO 58 GPI - INT PU* +3VSUS Title : System Setting
GPIO 59 Native USB_CON_OC01# +3VSUS ASUSTek Computer INC. NB1 Engineer: Leon
Size Project Name
GPIO 60 Native RTLAN_DSM_EN +3VSUS Rev
Custom K70IJ 1.0
Date: Wednesday, April 29, 2009 Sheet 2 of 96
5 4 3 2 1
5 4 3 2 1
AC mode will after EC_RST#
BAT Mode will after Press button
A/D_DOCK_IN
+5VLCM
+2.5VREF PCI_RST#
2 PWR_SW#
6 Power On
19
D D
SWITCH
EC_RST#
AC_BAT_SYS
+3VA
1 +3VA_EC 7 PM_PWRBTN# SLP_S4 PM_SUSC# 8
PWRBTN#
+5VA
3 5 PM_RSMRST# RSMRST#
SLP_S3 PM_SUSB# 10
VSUS_ON
EC 15 EC_CLK_EN VRMPWRGD
+1.5VSUS SUS_PWRGD
+3VSUS ICH9-M
IT8502 PM_PWROK CLK GEN
+5VSUS 4 SUSC_EC#
9
PWROK
ICH_CLKEN 16
PM_SUSC#
+12VSUS 8 17 CK_PWRGD VTTPWR_GD
10 PM_SUSB#
SUSB_EC# 11 CLPWROK
C C
CPU_VRON
13
12
ALL_SYSTEM_PWRGD
H_PWRGD
17
PLT_RST#
+0.9V
SUSC#_PWR PM_PWROK
+1.8V
+1.5V 14 19 18
9 +3V DDR_PWRGD
+5V
+12V CLPWROK 20
NB
VRM_PWRGD
H_CPURST# CPU
Cantiga GM
PWROK
B B
+VCCP
11 +1.5VS
SUSB#_PWR
+3VS
+5VS
PWRGD
+12VS
Power On Sequence
1 20
A A
CPU_VRON +VCORE
13
Title : Sequence
ASUSTeK COMPUTER INC Engineer: Leon
Size Project Name Rev
Custom K70IJ 1.0
Date: Wednesday, April 29, 2009 Sheet 3 of 96
5 4 3 2 1
5 4 3 2 1
+VCCP +VCCP 5,7,8,9,11,12,15,18,39,42,82
add test point
TPC26T 1 T0409
D +3VS D
U0401A
7 H_A#[16:3]
H_A#3 J4 H1 U0401B
A[3]# ADS# H_ADS# 7 7 H_D#[15:0] H_D#[47:32] 7
ADDR GROUP 0
ADDR GROUP 0
H_A#4 L5 E2 H_D#0 E22 Y22 H_D#32
A[4]# BNR# H_BNR# 7 D[0]# D[32]#
2
H_A#5 L4 G5 +VCCP H_D#1 F24 AB24 H_D#33
A[5]# BPRI# H_BPRI# 7 D[1]# D[33]#
H_A#6 K5 H_PROCHOT H_D#2 E26 V24 H_D#34
H_A#7 A[6]# R0421 H_D#3 D[2]# D[34]# H_D#35
M3 A[7]# DEFER# H5 H_DEFER# 7 G22 D[3]# D[35]# V26
1
DATA GRP 0
H_A#8 N2 F21 10KOhm H_D#4 F23 V23 H_D#36
A[8]# DRDY# H_DRDY# 7 D[4]# D[36]#
3
H_A#9 J1 E1 R0401 @ H_D#5 G25 T22 H_D#37
H_DBSY# 7
1
H_A#10 A[9]# DBSY# 56Ohm Q0402B H_D#6 D[5]# D[37]# H_D#38
N3 A[10]# E25 D[6]# D[38]# U25
H_A#11 P5 F1 UM6K1N 5 H_D#7 E23 U23 H_D#39
A[11]# BR0# H_BR0# 7 D[7]# D[39]#
H_A#12 P2 H_D#8 K24 Y25 H_D#40
2
4
A[12]# D[8]# D[40]#
6
DATA GRP 2
CONTROL
H_A#13 L2 D20 H_IERR# @ H_D#9 G24 W22 H_D#41
H_A#14 A[13]# IERR# Q0402A H_D#10 D[9]# D[41]# H_D#42
P4 A[14]# INIT# B3 H_INIT# 15 J24 D[10]# D[42]# Y23
H_A#15 P1 UM6K1N 2 H_D#11 J23 W24 H_D#43
A[15]# PM_THERM# 17,30 D[11]# D[43]#
H_A#16 R1 H4 H_D#12 H22 W25 H_D#44
H_LOCK# 7
1
A[16]# LOCK# TPC26T 1 T0420 H_D#13 D[12]# D[44]# H_D#45
7 H_ADSTB#0 M1 ADSTB[0]# @ H_D#14
F26 D[13]# D[45]# AA23
H_D#46
7 H_REQ#[4:0] RESET# C1 H_CPURST# 7 K22 D[14]# D[46]# AA24
H_REQ#0 K3 F3 H_D#15 H23 AB25 H_D#47
REQ[0]# RS[0]# H_RS#0 7 D[15]# D[47]#
H_REQ#1 H2 F4 J26 Y26
REQ[1]# RS[1]# H_RS#1 7 7 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 7
H_REQ#2 K2 G3 H26 AA26
REQ[2]# RS[2]# H_RS#2 7 7 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 7
H_REQ#3 J3 G2 H25 U22
REQ[3]# TRDY# H_TRDY# 7 7 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 7
H_REQ#4 L1 REQ[4]#
7 H_A#[35:17] HIT# G6 H_HIT# 7 7 H_D#[31:16] H_D#[63:48] 7
H_A#17 Y2 E4 D0401 @ H_D#16 N22 AE24 H_D#48
A[17]# HITM# H_HITM# 7 D[16]# D[48]#
H_A#18 U5 H_PROCHOT 1 2 H_D#17 K25 AD24 H_D#49
A[18]# PW RLIMIT# 30,88 D[17]# D[49]#
H_A#19 R3 AD4 XDP_BPM#0 1 T0410 TPC26T H_D#18 P26 AA21 H_D#50
A[19]# BPM[0]# D[18]# D[50]#
ADDR GROUP 1
ADDR GROUP 1
H_A#20 W6 AD3 XDP_BPM#1 RB751V-40 H_D#19 R23 AB22 H_D#51
H_A#21 A[20]# BPM[1]# XDP_BPM#2 T0411 TPC26T H_D#20 D[19]# D[51]# H_D#52
U4 A[21]# BPM[2]# AD1 1 L23 D[20]# D[52]# AB21
XDP/ITP SIGNALS
DATA GRP 1
H_A#22 Y5 AC4 XDP_BPM#3 1 T0412 TPC26T H_D#21 M24 AC26 H_D#53
H_A#23 A[22]# BPM[3]# H_PRDY# T0413 TPC26T H_D#22 D[21]# D[53]# H_D#54
C
U1 A[23]# PRDY# AC2 1 L22 D[22]# D[54]# AD20 C
H_A#24 H_PREQ# H_D#23 H_D#55
H_A#25
R4
T5
A[24]# PREQ# AC1
AC5 H_TCK AGTL+ I/O Voltage H_D#24
M23
P25
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