Service Manuals, User Guides, Schematic Diagrams or docs for : asus F8Tr-A8Z-X80Z
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5 4 3 2 1
Block Diagram
F8Tr/A8Z/X80Z 1.0 DC_IN & BAT CON
PAGE 60
AMD CPU VCORE
PAGE 80
SW & LED
D
S1G2 CPU DDR2 Dual Channel DDR2
PAGE 56 D
FAN + SENSOR 400-800 SO-DIMM x2
PAGE 50 PAGE 3,4,5,6 PAGE 7,8,9 SYSTEM PWR
PAGE 81
VGA Daughter BD HT 3.0
CLOCK BAT & CHARGER
2.6GHZ PAGE 88
ICS9LPRS479AGLFT
PAGE 29
Other PWR
PAGE 82, 83, 84, 85, 90, 91, 92, 93, 94
HDMI
PAGE 48 ATI AMD DDR2 800MHz
PCI-E x16
CRT RS780M PCI-E GLAN RJ11,RJ45 CON
PAGE 46 M82 RTL8111C
PAGE 33 PAGE 34
LVDS & INV PAGE 10,11,12,13,14,15
C
PAGE 45 TV Turner Card C
PAGE 70 PAGE 53
A-LINK Interface MINICARD
WLAN
PCI 33MHz PAGE 53
LPC 33MHz AMD NewCard/DebugCard
TPM PAGE 61
INTERNAL
PAGE 62
Azalia SB700
KEYBOARD
TOUCH PAD CardBus CARD READER
PAGE 31
CIR PAGE 20,21,22,23,24 RICOH R5C833
PAGE 55
EC PAGE 40,41
ITE/IT8752
BIOS SPI ROM PAGE 30,31
PAGE 30
B B
MIC IN
HP&SPDIF OUT PAGE 52
PAGE 43,44
OPAMP Azalia Codec
PAGE 38 Realtek/ALC663 38
PAGE 36, 37,
Internal MIC CON
USB 2.0 CON x4
PAGE 52 Daughter BD
PAGE 37
Azalia Camera USB HP&SPDIF OUT 1394
MDC Header PAGE 35
PAGE 68
CON
Fingerprint USB 2.0 CON x1 MIC IN
SATA ODD PAGE 63
PAGE 51
A PAGE 52 PAGE 67 A
Bluetooth
SATA HDD
PAGE 51 PAGE 42
Title : Block Diagram
Engineer: Wing_Cheng
ESATA ASUSTeK COMPUTER INC. NB6
Size Project Name Rev
PAGE 66 Custom A8Z/X80Z/F8Tr 0.1
PAGE 52 Date: Wednesday, March 12, 2008 Sheet 1 of 92
5 4 3 2 1
A B C D E
071226 RN0901,RN0908 to 0402
071227 add newcard wake# signal pull up p44
X3001 change to 1.3 high
remove PJP8307 because 12VSUS is not neet
change 3G LED circuit p56
del HDMI data signal ESD protect, add
HDMI DDC ESD protect
CRT ESD protect link to connect
prearrange 0ohm resister between
OS#_OC and NV_OVERT# P52
remove PD8301 PD8302
1 071228 remove HP DC blocking capacitors CE3800 CE3801 1
add CPU_THRMTRIP#_1.8V P5
add FAN0_PWM_R ESD protect p50
prearrange CPU_THRMTRIP# to SB700
071229 change sata TX serial resister from 4.99k to 4.99
add SB700 GPIO PU PD
memory swap
ADD KB cap for 3G
080102 add HDMI data signal ESD protect
divide CTR power from HDMI
correct smbus of lvds on page45
add colay 662 and 663
080103 change as word document
080104 add R4801
add netname:+5VSUS_REGIN,+3VSUS_REGIN,REF_15mil
delete net:+1.1V_REG(GPU)
change newcard pcie lane from 2 to 5
CHANGE L2001 P/N
0105 E-SATA pin10,pin11 link to GND
080105 ADD R6202,R6203
0105 ADD R5719,Q5718
0105 ADD R2123,2125,2113,2121 FOR SMbus
0105 change c4014 to 1uf
0107 ADD Q1202,R1228,R1229
2 0108 change R2008 to 22 ohm 2
0108 change fingerprint to usb13
0109 change pg30 pm_rsmrst# and PM_PWROK sequence
0109 add EMI cap on page 20 and page 29 for pci and 14M/48M clk
0109 add re-driver for E-SATA
0111 ADD C4208* FOR EMI
0111 ADD R5205 FOR EMI
0111 RESERVE PC9118
0111 delete R1203/R120/R1205
0111 add c5210
0111 add R2022 for safety
080303 the U and L of LVDS exchange p12
change Q9219B to Q5109B add R5104
C2901 C2902 CHANGE TO 27PF
add R1203 R1204 R1205
L4608 L4609 L4610 from 47OHM/100M to 47NH
add L4611 L4612 L4613 47NF
add C4621 C4622 C4623 5PF
C4618 C4619 C4620 from 47pf to 5pf and option change to /X
R4600 R4601 from 330HM to 27OHM
R4602 from 150OHM to 140OHM for RS780 A13
C4601 C4602 C4603 from 47pf to 6pf
del R6600 R6601 R6602 R6603
add R6609
U6601 R6604 CX6621 CX6622 CX6623 CX6624 option change to N/X
del R6605 R6606 R6607 R6608
3 add R6610 200OHM 3
add CX6617 CX6618 330pf and CX6619 CX66200.01uf
R2208 R2209 R2210 R2211 R2212 R2213 from 4.99OHM to 0OHM
D2001 R2022 optional change to /X, R2035 change to N/A
R4304 optionsl change to /X
R6106 optional change to N/A
R2120 optional change to N/A
080304 add R6611 optional to /X
CON5600 part number from 12G171000033 to 12G170000038
add C503 optional to /X
R3818 R3819 optional to /662
080305 add d2201 optional is /X
080306 del SIO P55
R2009 R2036 R2037 PN to 10G212000004010
del R2930
del SIO_SMI# net p22
del LPC_DRQ0# net p20
U5001 PN to 06G023026011
C5002 PN to 11G232110211150
add D5003 optonal is /X
080310 add C6700 C6701
R1222 optional to N/A
R1908, R1909, R1910, R1911, R1912, R1913,
R1914, R1915 change to 680OHM
C2018 C2019 C2020 C2017 C2021 C2022
change to 15pf,optional is N/A
4 4
add C5005 optional is /X
080312 add C5006 C5007 optional is /X
add C3407 C3408 optional is /X
5 5
Title :
ASUSTeK COMPUTER INC. NB1 Engineer:
Size Project Name Rev
Custom A8Z/X80Z/F8Tr 0.1
Date: Wednesday, March 12, 2008 Sheet 2 of 92
A B C D E
5 4 3 2 1
D D
1.5A
CPU_VLDT U0301A CPU_VLDT
D1
VLDT_A2
HT LINK VLDT_B1
AE2
D2 AE3
VLDT_A3 VLDT_B2
D3 AE4
VLDT_A1 VLDT_B3
D4 VLDT_A4 VLDT_B4 AE5
HT_CPU_RXD0 E3 AD1 HT_CPU_TXD0
HT_CPU_RXD#0 L0_CADIN_H[0] L0_CADOUT_H[0] HT_CPU_TXD#0
E2 AC1
HT_CPU_RXD1 L0_CADIN_L[0] L0_CADOUT_L[0] HT_CPU_TXD1
E1 AC2 HT_CPU_TXD[0..15] 10
HT_CPU_RXD#1 L0_CADIN_H[1] L0_CADOUT_H[1] HT_CPU_TXD#1
F1 AC3
HT_CPU_RXD2 L0_CADIN_L[1] L0_CADOUT_L[1] HT_CPU_TXD2
G3 L0_CADIN_H[2] L0_CADOUT_H[2] AB1
HT_CPU_RXD#2 G2 AA1 HT_CPU_TXD#2
L0_CADIN_L[2] L0_CADOUT_L[2] HT_CPU_TXD#[0..15] 10
HT_CPU_RXD3 G1 AA2 HT_CPU_TXD3
HT_CPU_RXD#3 L0_CADIN_H[3] L0_CADOUT_H[3] HT_CPU_TXD#3
H1 L0_CADIN_L[3] L0_CADOUT_L[3] AA3
HT_CPU_RXD4 J1 W2 HT_CPU_TXD4
HT_CPU_RXD#4 L0_CADIN_H[4] L0_CADOUT_H[4] HT_CPU_TXD#4
K1 W3
HT_CPU_RXD5 L0_CADIN_L[4] L0_CADOUT_L[4] HT_CPU_TXD5
L3 V1
HT_CPU_RXD#5 L0_CADIN_H[5] L0_CADOUT_H[5] HT_CPU_TXD#5
L2 U1
HT_CPU_RXD6 L0_CADIN_L[5] L0_CADOUT_L[5] HT_CPU_TXD6
L1 L0_CADIN_H[6] L0_CADOUT_H[6] U2
HT_CPU_RXD#6 M1 U3 HT_CPU_TXD#6
HT_CPU_RXD7 L0_CADIN_L[6] L0_CADOUT_L[6] HT_CPU_TXD7
N3 L0_CADIN_H[7] L0_CADOUT_H[7] T1
HT_CPU_RXD#7 N2 R1 HT_CPU_TXD#7
HT_CPU_RXD8 L0_CADIN_L[7] L0_CADOUT_L[7] HT_CPU_TXD8
E5 L0_CADIN_H[8] L0_CADOUT_H[8] AD4
HT_CPU_RXD#8 F5 AD3 HT_CPU_TXD#8
C HT_CPU_RXD9 L0_CADIN_L[8] L0_CADOUT_L[8] HT_CPU_TXD9 C
10 HT_CPU_RXD[0..15] F3 AD5
HT_CPU_RXD#9 L0_CADIN_H[9] L0_CADOUT_H[9] HT_CPU_TXD#9
F4 L0_CADIN_L[9] L0_CADOUT_L[9] AC5
HT_CPU_RXD10 G5 AB4 HT_CPU_TXD10
HT_CPU_RXD#10 L0_CADIN_H[10] L0_CADOUT_H[10] HT_CPU_TXD#10
10 HT_CPU_RXD#[0..15] H5 L0_CADIN_L[10] L0_CADOUT_L[10] AB3
HT_CPU_RXD11 H3 AB5 HT_CPU_TXD11
HT_CPU_RXD#11 L0_CADIN_H[11] L0_CADOUT_H[11] HT_CPU_TXD#11
H4 AA5
HT_CPU_RXD12 L0_CADIN_L[11] L0_CADOUT_L[11] HT_CPU_TXD12
K3 Y5
HT_CPU_RXD#12 L0_CADIN_H[12] L0_CADOUT_H[12] HT_CPU_TXD#12
K4 W5
HT_CPU_RXD13 L0_CADIN_L[12] L0_CADOUT_L[12] HT_CPU_TXD13
L5 L0_CADIN_H[13] L0_CADOUT_H[13] V4
HT_CPU_RXD#13 M5 V3 HT_CPU_TXD#13
HT_CPU_RXD14 L0_CADIN_L[13] L0_CADOUT_L[13] HT_CPU_TXD14
M3 V5
HT_CPU_RXD#14 L0_CADIN_H[14] L0_CADOUT_H[14] HT_CPU_TXD#14
M4 U5
HT_CPU_RXD15 L0_CADIN_L[14] L0_CADOUT_L[14] HT_CPU_TXD15
N5 T4
HT_CPU_RXD#15 L0_CADIN_H[15] L0_CADOUT_H[15] HT_CPU_TXD#15
P5 T3
L0_CADIN_L[15] L0_CADOUT_L[15]
HT_CPU_RX_CLK0 J3 Y1 HT_CPU_TX_CLK0
10 HT_CPU_RX_CLK0 L0_CLKIN_H[0] L0_CLKOUT_H[0] HT_CPU_TX_CLK0 10
HT_CPU_RX_CLK#0 J2 W1 HT_CPU_TX_CLK#0
10 HT_CPU_RX_CLK#0 L0_CLKIN_L[0] L0_CLKOUT_L[0] HT_CPU_TX_CLK#0 10
HT_CPU_RX_CLK1 J5 Y4 HT_CPU_TX_CLK1
10 HT_CPU_RX_CLK1 HT_CPU_RX_CLK#1 L0_CLKIN_H[1] L0_CLKOUT_H[1] HT_CPU_TX_CLK#1 HT_CPU_TX_CLK1 10
10 HT_CPU_RX_CLK#1 K5 Y3 HT_CPU_TX_CLK#1 10
L0_CLKIN_L[1] L0_CLKOUT_L[1]
HT_CPU_RX_CTL0 N1 R2 HT_CPU_TX_CTL0
10 HT_CPU_RX_CTL0 L0_CTLIN_H[0] L0_CTLOUT_H[0] HT_CPU_TX_CTL0 10
HT_CPU_RX_CTL#0 P1 R3 HT_CPU_TX_CTL#0
10 HT_CPU_RX_CTL#0 L0_CTLIN_L[0] L0_CTLOUT_L[0] HT_CPU_TX_CTL#0 10
HT_CPU_RX_CTL1 P3 T5 HT_CPU_TX_CTL1
10 HT_CPU_RX_CTL1 HT_CPU_RX_CTL#1 L0_CTLIN_H[1] L0_CTLOUT_H[1] HT_CPU_TX_CTL#1 HT_CPU_TX_CTL1 10
10 HT_CPU_RX_CTL#1 P4 R5 HT_CPU_TX_CTL#1 10
L0_CTLIN_L[1] L0_CTLOUT_L[1]
SOCKET638
12G011306384 071113
B Do not cross plane. B
+1.2VS
Irat=2A
CPU_VLDT
120Ohm/100Mhz
L0301
C0302 C0306
C0301 C0303 C0304 C0305 C0307
4.7UF/6.3V 4.7UF/6.3V 4.7UF/6.3V 0.22UF/6.3V 0.22UF/6.3V 180PF/50V
C 26 D 26 E 26 F 26 G 26 H 26 J2 6 K 26 L2 6 M 26 N 26 P 26 R 26 T 26 U 26 V 26 W2 6 Y 26 A A2 6 A B2 6 AC 6
2 AD 6
2
B 25 C 25 D 25 E 25 F 25 G 25 H 25 J2 5 K 25 L2 5 M 25 N 25 P 25 R 25 T 25 U 25 V 25 W2 5 Y 25 A A2 5 A B2 5 AC 5
2 AD 5
2 A E2 5
180PF/50V
A 24 B 24 C 24 D 24 E 24 F 24 G 24 H 24 J2 4 K 24 L2 4 M 24 N 24 P 24 R 24 T 24 U 24 V 24 W2 4 Y 24 A A2 4 A B2 4 AC 4
2 AD 4
2 A E2 4 A F2 4
A 23 B 23 C 23 D 23 E 23 F 23 G 23 H 23 J2 3 K 23 L2 3 M 23 N 23 P 23 R 23 T 23 U 23 V 23 W2 3 Y 23 A A2 3 A B2 3 AC 3
2 AD 3
2 A E2 3 A F2 3
A 22 B 22 C 22 D 22 E 22 F 22 G 22 H 22 J2 2 K 22 L2 2 M 22 N 22 P 22 R 22 T 22 U 22 V 22 W2 2 Y 22 A A2 2 A B2 2 AC 2
2 AD 2
2 A E2 2 A F2 2
GND A 21
A 20
B 21
B 20
C 21
C 20
D 21
D 20
E 21
E 20
F 21
F 20
G 21 H 21
H 20
J2 1
J2 0
K 21
K 20
L2 1
L2 0
M 21
M 20
N 21
N 20
P 21
P 20
R 21
R 20
T 21
T 20
U 21
U 20
V 21
V 20
W2 1 Y 21
Y 20
A A2 1
A A2 0
A B2 1
A B2 0
2
AC 1
AC 0
2
2
AD 1
AD 0
2
A E2 1
A E2 0
A F2 1
A F2 0
A 19 B 19 C 19 D 19 E 19 F 19 H 19 J1 9 K 19 L1 9 M 19 N 19 P 19 R 19 T 19 U 19 V 19 Y 19 A A1 9 A B1 9 AC 9
1 AD 9
1 A E1 9 A F1 9
A 18 B 18 C 18 D 18 E 18 F 18 G 18 H 18 J1 8 K 18 L1 8 M 18 N 18 P 18 R 18 T 18 U 18 V 18 W1 8 Y 18 A A1 8 A B1 8 AC 8
1 AD 8
1 A E1 8 A F1 8
A 17 B 17 C 17 D 17 E 17 F 17 G 17 H 17 J1 7 K 17 L1 7 M 17 N 17 P 17 R 17 T 17 U 17 V 17 W1 7 Y 17 A A1 7 A B1 7 AC 7
1 AD 7
1 A E1 7 A F1 7
A A 16 B 16 C 16 D 16 E 16 F 16 G 16 H 16 J1 6 K 16 L1 6 M 16 N 16 P 16 R 16 T 16 U 16 V 16 W1 6 Y 16 A A1 6 A B1 6 AC 6
1 AD 6
1 A E1 6 A F1 6
A
GND A 15
A 14
B 15
B 14
C 15
C 14
D 15
D 14
E 15
E 14
F 15
F 14
G 15
G 14
H 15
H 14
J1 5
J1 4
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