Service Manuals, User Guides, Schematic Diagrams or docs for : asus M9V
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5 4 3 2 1
DOTHAN/ALVISO-GM(PM)/ATI M24 BLOCK DIAGRAM
SUB-BOARD CLOCK
CPU FAN & THERMAL
SENSOR
GENERATOR DOTHAN ADT7473
D
ICS954213 PAGE 6
478 uFCPGA D
PAGE 7
INSTANT KEY PAGE 3,4,5
BOARD
CRT CN PAGE 24
FSB
ATI
AUDIO DJ
BOARD
TV OUT PAGE 24 M24-C PCI-E
PAGE 14,15,16,17
ALVISO DDRII SDRAM 400/533MHz
LCD CN & INVERTER PAGE 25 GM(PM)CH
MIC 1257 uFCBGA
BOARD
ONBOARD
PAGE 8,9,10,11,12,13 ONBOARD STANDARD
DDR
DDRII DDRII
128MB PAGE 18,19
DMI 512MB PAGE 20,21 DIMM PAGE 22,23
C PAGE 42 C
RTC CN
SM_BUS
PAGE 42
PAGE 44 POWER UP
DC IN
POWER USB 2.0 ICH6-M RESET
CIRCUIT PAGE 29
609 uFCBGA
PCI BUS 3.3V, 33MHz
CMOS
VCORE MODULE IDE
PAGE 48
PAGE 33
BUS PAGE 20,21,22
CARDBUS LAN MINI-PCI
SYSTEM 3VO/5VO
RICOH R5C841 REALTEK 8101L 802.11 a/b/g
PAGE 49
PAGE 34,35,36 PAGE 38 PAGE 40
BLUETOOTH AZALIA
1.2V/1.5V/1.8V/1.05V MODULE LPC ADI AD1986A
PAGE 50 PAGE 33
33MHz PAGE 30
1394 LAN IO
PAGE 36 PAGE 39
B
1.5VA/0.9VS B
PAGE 51
USB 2.0 * 4 PHONE
PAGE 43
JACK
BATLOW/SD# KEYBOARD FWH PAGE 31 ONE
PAGE 52
CONTROLLER PAGE 44
PCMCIA
MITSUBISHI M38857 SLOT
CHARGE DEBUG PAGE 45
AUDIO PAGE 37
PAGE 53
PORT AMP &
PAGE 5 TPM INT.
BAT CON CARDBUS
PAGE 54 PAGE 44 SPK PAGE 32
POWER
PIC16C54 HDD CN INTERNAL SWITCH
PAGE 55
PAGE 41
KB & TP MIC PRE R5531
PAGE 46
AMP & MIC PAGE 37
LOAD Switch JACK
PAGE 56
PAGE 33
ODD CN 4 IN 1 MEMORY
VGA VCORE PAGE 41 Audio DJ CARD
PAGE 57
A MDC READER A
HEARDER SD/MMC/MS/XD
PAGE 47 PAGE 39 PAGE 37
REVISION DATE: Thursday, September 08, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
PROJECT: M9V LIBRARY DATE :
2.1 SHEET 1 OF 61 BLOCK DIAGRAM
5 4 3 2 1
A B C D E
PAGE Content PAGE Content
M9V PAGE REF.
1 Block Diagram 53 CHARGE
2 Page Reference 54 BAT CONNECT
1
3 Dothan Main (1) 55 PIC16C54 & PRO_CIR 1
4 Dothan Power & GND (2) 56 LOAD SWITCH
5 Cpu Cap & Debug Card 57 M24-C - VGA VCORE
6 Clock Generator 58 Power Flowchart
7 Fan & Thermal Sensor 59 Power History
8 Alviso GM(PM)CH - Host (1) 60 Revision History
9 Alviso GM(PM)CH - PCI-E (2)
10 Alviso GM(PM)CH - DDR (3)
11 Alviso GM(PM)CH - Power (4)
12 Alviso GM(PM)CH - GND (5)
13 GM(PM)CH Strapping
14 M24-C - Main (1)
2 15 M24-C - Memory Interface (2) 2
16 M24-C - Power (3)
17 M24-C - Straping (4)
18 M24-C - DDR Memory A
19 M24-C - DDR Memory B
20 DDR2 (1)
21 DDR2 (2)
22 Standard DDR2 SO-DIMM
23 DDR2 Address Termination
24 CRT & TV OUT
25 LCD & Inverter
3
26 ICH6M - LPC & IDE (1) 3
27 ICH6M - USB & PCI-E & PMIO (2)
28 ICH6M - PWR & GND (3)
29 Reset Circuit
30 Azalia AD1986A
31 PHONE JACK
32 Audio AMP & INT SPK
33 MIC PRE-AMP & MIC JACK & ExtCN
34 CardBus RICOH 5C841/PCI_B
35 CardBus RICOH 5C841/PCI_A
36 CardBus RICOH 5C841/PCI_C
37 Cardbus & CardReader & PwrSw
4 38 LAN RealTek-RTL8101L 4
39 LAN IO & MDC
40 MiniPCI
41 HDD CN & CDROM CN
42 SM_BUS & RTC CN
43 4*USB2.0 Conn
44 DCIN JACK & FWH & TPM
45 Keyboard Controller (M3885)
46 LEDs & Internal KB & TP
47 Audio DJ
48 VCORE
5
49 SYSTEM 5
50 2.5V & 1.5V & 1.8V & 1.05V
51 1.5VA & DDR2 & 3VALWAYS_P
52 BATLOW/SD#
REVISION DATE: Thursday, September 08, 2005 DESCRIPTION: SCHEMATIC FILE NAME : DESIGN ENGINEER :
ASUS PROJECT: M9V 2.1 SHEET 2 OF 61 PAGE REFERENCE LIBRARY DATE :
A B C D E
5 4 3 2 1
+VCCP
H_D#[0:63] 8
1
R623
U49A
8 H_A#[3:16]
U49B 56Ohm H_D#15 C25 Y25 H_D#47
H_A#16 H_D#14 D[15]# D[47]# H_D#46
AA2 A[16]# ADS# N2 H_ADS# 8 E23 D[14]# D[46]# AA26
H_A#15 TP91 H_D#13 H_D#45
2
Y3 A[15]# PRDY# A10 1 B23 D[13]# D[45]# Y23
H_A#14 AA3 B10 1 TP90 H_D#12 C26 V26 H_D#44
H_A#13 A[14]# PREQ# H_D#11 D[12]# D[44]# H_D#43
U1 A[13]# E24 D[11]# D[43]# U25
H_A#12 Y1 L1 H_D#10 D24 V24 H_D#42
A[12]# BNR# H_BNR# 8 D[10]# D[42]#
DATA GROUP 0
H_A#11 H_D#9 H_D#41
2
Y4 J3 H_BPRI# 8 B24 U26
ADDRESS GROUP 0
D H_A#10 A[11]# BPRI# H_D#8 D[9]# D[41]# H_D#40 D
W2 C20 AA23
DATA GROUP
H_A#9 A[10]# H_D#7 D[8]# D[40]# H_D#39
T4 A[9]# B20 D[7]# D[39]# R23
H_A#8 W1 A7 1 TP89 H_D#6 A21 R26 H_D#38
H_A#7 A[8]# DBR# H_D#5 D[6]# D[38]# H_D#37
V2 A[7]# B26 D[5]# D[37]# R24
H_A#6 R3 H_D#4 A24 V23 H_D#36
H_A#5 A[6]# H_D#3 D[4]# D[36]# H_D#35
V3 A[5]# B21 D[3]# D[35]# U23
H_A#4 U4 L4 H_D#2 A22 T25 H_D#34
A[4]# DEFER# H_DEFER# 8 D[2]# D[34]#
H_A#3 P4 H2 H_D#1 A25 AA24 H_D#33
A[3]# DRDY# H_DRDY# 8 D[1]# D[33]#
U3 M2 H_D#0 A19 Y26 H_D#32
8 H_ADSTB#0 ADSTB[0]# DBSY# H_DBSY# 8 D[0]# D[32]#
H_REQ#4 T1 D25 T24
REQ[4]# 8 H_DINV#0 DINV[0]# DINV[2]# H_DINV#2 8
H_REQ#3 P1 C23 W25
REQ[3]# 8 H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 8
H_REQ#2 T2 C22 W24
REQ[2]# +VCCP 8 H_DSTBP#0 DSTBP[0]# DSTBP[2]# H_DSTBP#2 8
H_REQ#1 P3
H_REQ#0 REQ[1]# H_D#31 H_D#63
R2 REQ[0]# K25 D[31]# D[63]# AF26
N4 H_D#30 N25 AF22 H_D#62
H_BREQ#0 8
CONTROL
BR0# H_D#29 D[30]# D[62]# H_D#61
8 H_REQ#[0:4] H26 D[29]# D[61]# AF25
H_D#28 M25 AD21 H_D#60
H_IERR# R616 D[28]# D[60]#
8 H_A#[17:31] IERR# A4 1 2 56Ohm H_D#27 N24 D[27]# D[59]# AE21 H_D#59
H_D#26 L26 AF20 H_D#58
3
D[26]# D[58]#
DATA GROUP 1
H_A#31 AF1 H_D#25 J25 AD24 H_D#57
H_A#30 A[31]# H_D#24 D[25]# D[57]# H_D#56
DATA GROUP
AE1 A[30]# INIT# B5 H_INIT# 26 M23 D[24]# D[56]# AF23
H_A#29 AF3 H_D#23 J23 AE22 H_D#55
H_A#28 A[29]# +VCCP H_D#22 D[23]# D[55]# H_D#54
AD6 G24 AD23
ADDRESS GROUP 1
H_A#27 A[28]# H_D#21 D[22]# D[54]# H_D#53
AE2 A[27]# LOCK# J2 H_LOCK# 8 F25 D[21]# D[53]# AC25
H_A#26 AD5 H_D#20 H24 AC22 H_D#52
H_A#25 A[26]# H_D#19 D[20]# D[52]# H_D#51
AC6 A[25]# M26 D[19]# D[51]# AC20
H_A#24 AB4 H_D#18 L23 AB24 H_D#50
H_A#23 A[24]# R631 1 D[18]# D[50]#
AD2 A[23]# 2 54.9Ohm H_D#17 G25 D[17]# D[49]# AC23 H_D#49
H_A#22 AE4 @ H_D#16 H23 AB25 H_D#48
H_A#21 A[22]# D[16]# D[48]#
AD3 A[21]# RESET# B11 H_CPURST# 8 8 H_DINV#1 J26 DINV[1]# DINV[3]# AD20 H_DINV#3 8
H_A#20 AC3 L2 H_RS#2 K24 AE24
A[20]# RS[2]# 8 H_DSTBN#1 DSTBN[1]# DSTBN[3]# H_DSTBN#3 8
H_A#19 AC7 K1 H_RS#1 L24 AE25
C A[19]# RS[1]# 8 H_DSTBP#1 DSTBP[1]# DSTBP[3]# H_DSTBP#3 8 C
H_A#18 AC4 H1 H_RS#0
H_A#17 A[18]# RS[0]# SOCKET479P
AF4 A[17]# H_RS#[0:2] 8
8 H_ADSTB#1 AE5 ADSTB[1]# TRDY# M3 H_TRDY# 8
HIT# K3 H_HIT# 8
8 H_DPWR# C19 DPWR# HITM# K4 H_HITM# 8
SOCKET479P
U49C
6 CLK_CPU_BCLK B15 BCLK[0]
B14
HOSTCLK
6 CLK_CPU_BCLK# BCLK[1]
R634 1 2 49.9Ohm A16 AB1 H_COMP3 R216 1 2 54.9Ohm R5,R7(COMP3,COMP1) should be placed within 0.5" R170 0Ohm @
R635 1 ITP_CLK[0] COMP[3]
2 49.9Ohm A15 ITP_CLK[1] COMP[2] AB2 H_COMP2 R215 1 2 27.4Ohm of processor pin. Traces shold be 55 ohm +/-15%. 1 2 +V1.8S_PROC_VCCA1
P26 H_COMP1 R661 1 2 54.9Ohm
COMP[1]
1
C2 P25 H_COMP0 R660 1 2 27.4Ohm R6,R8(COMP2,COMP0) should be placed within 0.5" C146
26 H_A20M# A20M# COMP[0]
26 H_FERR# D3 FERR# of processor pin. Traces shold be 27.4 ohm +/-15%.
+V1.8S_PROC
LEGACY CPU
A3 1UF/6.3V @
26 H_IGNNE# IGNNE#
2
26 H_DPSLP# B7 DPSLP# BPM[3]# C9
A6 A9 R581 0Ohm @ R222 0Ohm @
8,26 H_CPUSLP# SLP# BPM[2]# +VCCP
26 H_INTR D1 LINT0 BPM[1]# B8 +1.8VS 1 2 1 2 +V1.8S_PROC_VCCA2
5 H_NMI D4 LINT1 BPM[0]# C8
1
1
1
B4 C670 C672 C162
26 H_SMI# SMI#
1
R618 1 2 0Ohm C6 R176 0Ohm
26 H_STPCLK# STPCLK#
1 2 0.01UF/10V 10UF/6.3V 1UF/6.3V @
+1.5VS
R665
2
2
2
26 H_PWRGD E4 PWRGOOD GTLREF[3] AC1
G1 1KOhm R664 0Ohm @
GTLREF[2] H_DPRSTP# 26
H_VID5 H4 E26 1 2
VID[5] GTLREF[1] +V1.8S_PROC_VCCA3
H_VID4 GT_REF0
2
G4 VID[4] GTLREF[0] AD26
1
H_VID3 G3 C680
VID[3]
1
B H_VID2 F3 B
H_VID1 VID[2] R666 0.1uF/10V @
F2 VID[1]
H_VID0 R617 1 2 1KOhm @ 2KOhm +VCCP +VCCP +VCCP +VCCP
2
E2 VID[0] TEST1 C5
F23 R273 1 2 1KOhm @
TEST2
MISC
+VCCP
1
1
1
1
+V1.8S_PROC_VCCA3
2
AC26 VCCA[3]
+V1.8S_PROC_VCCA2 N1 R251 R640 R620 R223
+V1.8S_PROC_VCCA1 VCCA[2] R630 1
B1 VCCA[1] TCK A13 2 27Ohm
+V1.8S_PROC F26 C12 R624 1 2 150Ohm 200Ohm 56Ohm 56Ohm 56Ohm
VCCA[0] TDI R629 1
TDO A12 2 54.9Ohm @ @ @
2
2
2
2
7 CPU_THERM_DA B18 THERMDA TMS C11 H_TMS 5
A18 B13 H_PWRGD
7 CPU_THERM_DC THERMDC TRST# H_TRST# 5
C17 H_PROCHOT_S#
9,26 PM_THRMTRIP# H_PROCHOT_S# THERMTRIP# H_DPSLP#
B17 PROCHOT#
AE7 R252 1 2 54.9Ohm @ H_DPRSTP#
R218 1 VCCSENSE
48 PM_PSI# 2 0Ohm E1 RSVD5
R636 1 2 0Ohm C16
6 CPU_BSEL0 RSVD4
C3 RSVD3
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