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5 4 3 2 1
M50S / X55S
BLOCK DIAGRAM CPU
Clock Generator Discharge Circuit
Page 57
ICS ICS9LPR363
MEROM
Page 29
Reset Circuit
Page 3~5 Page 32
D D
Thermal Sensor
LCD Panel Maxim MAX6657 Sequnce Logic
Page 50 Page 68
Page 45
CRT PWM Fan DC Conn.
Page 46 MXM North Bridge Page 50 Page 60
Intel 965PM DDR2 So-DIMM
TV-Out Page 7~9 Skew Holes Battery Conn.
Page 70
Page 47 Page 10~16 Page 65 Page 60
HDMI
Page 48
ODD MiniCard
Page 51 WLAN
C
Power C
Page 53
HDD VCORE
Page 51 MiniCard Page 80
Robson
1394
CardReader 1394 Page 58 System
Page 41
Ricoh R5C833 Page 81
Cardreader Page 40~41
GigaLAN
1.5VS & 1.05VS
Page 42 Marvell 88E8055 Transformer RJ45/RJ11
South Bridge Page 33 Page 34 Page 34
Page 82
TPM 1.2 ICH8-M
Page 62 DDR & VTT
eSATA Page 83
Debug Conn. JMicron JMB360
Page 44 Page 66 +1.25VS
B B
Touchpad Page 84
Page 31
EC ExpressCard
Page 43 Charger
ITE IT8752E
Keyboard Page 30
USB/eSATA Page 88
Page 66
Page 31 Detect
CIR SPI ROM
Page 31 Page 30
USB Port MiniCard Page 90
Page 45 WWAN
Load Switch
Page 67
Azalia MDC USB Port Page 91
Page 35 Page 65
MiniCard Power Protect
Audio Amp
Azalia Codec USB Port TV Tuner Page 92
Page 37
Realtek ALC888S Page 65 Page 64
Jack Page 36
A
Page 95
Fingerprint Bluetooth A
Page 63 Page 61
Array Mic.DSP
Array Mic CMOS Camera
Fortemedia FM2010 Title : Block Diagram
Page 45 Page 45
Page 38 Page 20~23 ASUSTeK COMPUTER INC. NB1 Engineer: John Hung
Size Project Name Rev
Custom 2.0
Date: Monday, September 03, 2007 Sheet 1 of 95
5 4 3 2 1
5 4 3 2 1
ICH8-M GPIO SETTING EC IT8752E GPIO SETTING 965GM/PM co-layout option:
Pin Pin Name Signal Name Type Pin Pin Name Signal Name Type Pin Pin Name Signal Name Type
AG12 BM_BUSY#/GPIO0 PM_BMBUSY# I 28 PWM0/GPA0 PWR_LED_UP# O 105 CLKRUN#/GPH0 PM_CLKRUN# I/O 965PM
AJ8 TACH1/GPIO1 BT_DECT# I 29 PWM1/GPA1 CHG_LED_UP# O 106 CRX1/GPH1 3G_ON# O
Change:
F8 PIRQE#/GPIO2 PCI_INTE# I/OD 32 PWM2/GPA2 107 CTX1/GPH2 3G_LED_ON# O U1001 to 965PM, U3601 to ALC888S
D D
G11 PIRQF#/GPIO3 PCI_INTF# I/OD 33 PWM3/GPA3 108 GPH3 BAT_LEARN I/O R1213~R1219 to 0ohm
C1406, C1501~C1504, C1506~C1507, C1510, C1514 to 0ohm
F12 PIRQG#/GPIO4 PCI_INTG# I/OD 34 PWM4/GPA4 LCD_BL_PWM O 109 GPH4
B3 PIRQH#/GPIO5 PCI_INTH# I/OD 35 PWM5/GPA5 FAN_PWM O 110 GPH5 NUM_LED O Mount:
D4801~D4803
AJ9 TACH2/GPIO6 36 PWM6/GPA6 111 GPH6 CAP_LED O
F4801
AH9 TACH3/GPIO7 WLAN_LED_ON O 38 PWM7/GPA7 74 ADC0/GPI0 NV_OVERT# I J4801, J7001
AE16 GPIO8 EXT_SMI# I 122 RXD/GPB0 CHG_EN# O 75 ADC1/GPI1 SUS_PWRGD I H7001~H7004
Q4801
AG19 WOL_EN/GPIO9 123 TXD/GPB1 PRECHG O 76 ADC2/GPI2 ALL_SYS_PWRGD I R1112~R1117, R1203~R1212, R1502, R2910, R3618~R3620, R4801~R4804
AJ24 CLGPIO1/GPIO10 139 CTX0/GPB2 77 ADC3/GPI3 CPU_PWRGD I RX2901~RX2902, RX4801~RX4810
CX1201~CX1232
AG22 SMBALERT#/GPIO11 SMB_ALERT# I 124 SMCLK0/GPB3 SMB0_CLK I/O 78 ADC4/GPI4 PWR_MON I
AC19 GPIO12 EXT_SCI# I 125 SMDAT0/GPB4 SMB0_DAT I/O 79 ADC5/GPI5 ALS_DA I Un-mount:
R1202, R1401~R1403, R1501, R1503~R1505, R2909, R3621, R7001~R7008
AH21 GLAN_DOCK#/GPIO13 142 GA20/GPB5 A20GATE O 80 ADC6/GPI6
RN7001~RN7011
AF22 CLGPIO2/GPIO14 4 KBRST#/GPB6 RC_IN# O 81 ADC7/GPI7 RNX1201, RNX2901, RNX2915
AE20 STP_PCI#/GPIO15 STP_PCI# I/O 126 GPB7 PM_RSMRST# O 84 DAC0/GPJ0 EC_CLK_EN L1501~L1505
C1404~C1405, C1407~C1409, C1505, C1509, C1511~C1513
AJ14 DPRSLPVR/GPIO16 PM_DPRSLPVR O 133 CRX0/GPC0 CRX0 I 85 DAC1/GPJ1 PM_PWROK CE1404, CE1501~CE1503
AG8 TACH0/GPIO17 WLAN_ON# O 129 SMCLK1/GPC1 SMB1_CLK I/O 86 DAC1/GPJ2
C C
AH12 GPIO18 130 SMDAT1/GPC2 SMB1_DAT I/O 87 DAC1/GPJ3
AJ10 GPIO19/SATA1GP 64 GPC3 PM_PWRBTN# O 88 DAC1/GPJ4 965GM
AE11 GPIO20 BT_LED_ON O 136 WUI2/GPC4 AC_IN_OC# I 89 DAC1/GPJ5
Change:
AJ12 SATA0GP/GPIO21 65 GPC5 OP_SD# O 15 GPK0 U1001 to 965GM
AG10 SCLOCK/GPIO22 140 WUI3/GPC6 BAT1_IN_OC# I 16 GPK1 R1213~R1218 to 150ohm
R1219 to 1.3Kohm
E6 LDRQ1#/GPIO23 20 GPC7 RFON_SW# I 17 GPK2
AJ27 CLGPIO0/GPIO24 22 WUI0/GPD0 PWRLIMIT# I 18 GPK3 Un-mount:
D4801~D4803
AG18 STP_CPU#/GPIO25 STP_CPU# O 25 WUI1/GPD1 PM_SUSC# I 48 GPK4
F4801
AH27 S4_STATE#/GPIO26 26 WUI4/GPD2 BUF_PLT_RST# I 49 GPK5 J4801, J7001
AH25 QRT_STATE0/GPIO27 BT_ON# O 27 ECSCI#/GPD3 EXT_SCI# O 62 GPK6 H7001~H7004
Q4801
AD16 QRT_STATE1/GPIO28 CB_SD# O 19 GPD4 EXT_SMI# O 63 GPK7 R1112~R1117, R1203~R1212, R1502, R2910, R3618~R3620, R4801~R4804
AG17 OC#5/GPIO29 INT_USB_OC# I 37 GPD5 LCD_BACKOFF# O 90 GPL0 RX2901~RX2902, RX4801~RX4810
CX1201~CX1232
AD12 OC#6/GPIO30 INT_USB_OC# I 53 TACH0 / GPD6 FAN0_TACH I 91 GPL1
AJ18 OC#7/GPIO31 INT_USB_OC# I 54 GPD7 92 GPL2 Mount:
R1202, R1401~R1403, R1501, R1503~R1505, R2909, R3621, R7001~R7008
AH11 CLKRUN#/GPIO32 PM_CLKRUN# O 23 GPE0 VSUS_ON O 93 GPL3
RN7001~RN7011
B AE10 AZ_DOCK_EN#/GPIO33 94 GPE1 SUSC_EC# O 119 GPL4 RNX1201, RNX2901, RNX2915 B
AG14 AZ_DOCK_RST#/GPIO34 95 GPE2 SUSB_EC# O 120 GPL5 L1501~L1505
C1404~C1409, C1501~C1507, C1509~C1514
AG13 SATACLKREQ#/GPIO35 96 GPE3 CPU_VRON O 134 GPL6 CE1404, CE1501~CE1503
AF11 SATA2GP/GPIO36 EMAIL_LED# O 141 PWRSW/GPE4 PWR_SW# I 135 GPL7
AG11 SATA3GP/GPIO37 PCB_ID0 I 39 WUI5/GPE5 BAT2_IN_OC# I
AF9 SLOAD/GPIO38 PCB_ID1 I 21 GPE6 LID_SW# I
AJ11 SDATAOUT0/GPIO39 PCB_ID2 I 24 GPE7 INSTANT_ON# I
AG16 OC#1/GPIO40 USB_CON01_OC# I 97 PS2CLK0/GPF0
AG15 OC#2/GPIO41 USB_CON23_OC# I 98 PS2DAT0/GPF1 COLOREN# I
AE15 OC#3/GPIO42 USB_CON23_OC# I 99 PS2CLK1/GPF2 MARATHON# I
AF15 OC#4/GPIO43 NEWCARD_OC# I 100 PS2DAT1/GPF3 DISTP# I
AD10 SATAOUT1/GPIO48 101 PS2CLK2/GPF4 TP_CLK I/O
AG29 CPUPWRGD/GPIO49 H_PWRGD O 102 PS2DAT2/GPF5 TP_DAT I/O
E18 REQ1#/GPIO50 PCI_REQ#1 I/O 131 SMCLK2/GPF6 THRO_CPU O
C18 GNT1#/GPIO51 132 SMDAT2/GPF7 TP_LED O
A B19 REQ2#/GPIO52 PCI_REQ#2 I/O 118 WUI7/GPG0 A
F18 GNT2#/GPIO53 121 GPG1 PM_SUSB# I
A11 REQ3#/GPIO54 PCI_REQ#3 I/O 112 GPG2
C10 GNT3#/GPIO55 116 GPG6
Title : System Setting
ASUSTeK COMPUTER INC. NB1 Engineer: John Hung
Size Project Name Rev
Custom 2.0
Date: Monday, September 03, 2007 Sheet 2 of 95
5 4 3 2 1
5 4 3 2 1
Main Board
10 H_A#[16:3] U0301A 10 H_D#[15:0] U0301B H_D#[47:32] 10
H_A#3 J4 H1 H_ADS# 10 H_D#0 E22 Y22 H_D#32
H_A#4 A[3]# ADS# H_D#1 D[0]# D[32]# H_D#33
D L5 A[4]# BNR# E2 H_BNR# 10 F24 D[1]# D[33]# AB24 D
H_A#5 L4 G5 +VCCP H_D#2 E26 V24 H_D#34
A[5]# BPRI# H_BPRI# 10 D[2]# D[34]#
H_A#6 K5 H_D#3 G22 V26 H_D#35
H_A#7 A[6]# H_D#4 D[3]# D[35]# H_D#36
M3 A[7]# DEFER# H5 H_DEFER# 10 F23 D[4]# D[36]# V23
H_A#8 N2 F21 H_DRDY# 10 H_D#5 G25 T22 H_D#37
H_A#9 A[8]# DRDY# R0301 H_D#6 D[5]# D[37]# H_D#38
J1 A[9]# DBSY# E1 H_DBSY# 10 E25 D[6]# D[38]# U25
H_A#10 N3 56Ohm H_D#7 E23 U23 H_D#39
H_A#11 A[10]# H_D#8 D[7]# D[39]# H_D#40
P5 A[11]# BR0# F1 H_BR0# 10 K24 D[8]# D[40]# Y25
H_A#12 P2 H_D#9 G24 W22 H_D#41
H_A#13 A[12]# H_IERR# H_D#10 D[9]# D[41]# H_D#42
L2 A[13]# IERR# D20 J24 D[10]# D[42]# Y23
H_A#14 P4 B3 H_D#11 J23 W24 H_D#43
A[14]# INIT# H_INIT# 20 D[11]# D[43]#
H_A#15 P1 H_D#12 H22 W25 H_D#44
H_A#16 A[15]# H_D#13 D[12]# D[44]# H_D#45
R1 A[16]# LOCK# H4 H_LOCK# 10 F26 D[13]# D[45]# AA23
10 H_ADSTB#0 M1 H_D#14 K22 AA24 H_D#46
ADSTB[0]# H_D#15 D[14]# D[46]# H_D#47
10 H_REQ#[4:0] RESET# C1 H_CPURST# 10 H23 D[15]# D[47]# AB25
H_REQ#0 K3 F3 H_RS#0 10 10 H_DSTBN#0 J26 Y26 H_DSTBN#2 10
H_REQ#1 REQ[0]# RS[0]# DSTBN[0]# DSTBN[2]#
H2 REQ[1]# RS[1]# F4 H_RS#1 10 10 H_DSTBP#0 H26 DSTBP[0]# DSTBP[2]# AA26 H_DSTBP#2 10
H_REQ#2 K2 G3 H_RS#2 10 10 H_DINV#0 H25 U22 H_DINV#2 10
H_REQ#3 REQ[2]# RS[2]# DINV[0]# DINV[2]#
J3 REQ[3]# TRDY# G2 H_TRDY# 10
H_REQ#4 L1 REQ[4]# 10 H_D#[31:16] H_D#[63:48] 10
10 H_A#[35:17] G6 H_HIT# 10 H_D#16 N22 AE24 H_D#48
H_A#17 HIT# H_D#17 D[16]# D[48]# H_D#49
Y2 A[17]# HITM# E4 H_HITM# 10 K25 D[17]# D[49]# AD24
H_A#18 U5 H_D#18 P26 AA21 H_D#50
H_A#19 A[18]# H_D#19 D[18]# D[50]# H_D#51
R3 A[19]# BPM[0]# AD4 R23 D[19]# D[51]# AB22
H_A#20 H_D#20 H_D#52
H_A#21
W6
U4
A[20]# BPM[1]# AD3
AD1
AGTL+ I/O H_D#21
L23
M24
D[20]# D[52]# AB21
AC26 H_D#53
A[21]# BPM[2]# D[21]# D[53]#
H_A#22
H_A#23
Y5 A[22]# BPM[3]# AC4 Voltage H_D#22
H_D#23
L22 D[22]# D[54]# AD20 H_D#54
H_D#55
U1 A[23]# PRDY# AC2 M23 D[23]# D[55]# AE22
H_A#24 R4 A[24]# PREQ# AC1 H_PREQ# Reference H_D#24 P25 D[24]# D[56]# AF23 H_D#56
H_A#25 T5 AC5 H_TCK H_D#25 P23 AC25 H_D#57
H_A#26 A[25]# TCK H_TDI H_D#26 D[25]# D[57]# H_D#58
C
T3 A[26]# TDI AA6 P22 D[26]# D[58]# AE21 C
H_A#27 W2 AB3 +VCCP +VCCP H_D#27 T24 AD21 H_D#59
H_A#28 A[27]# TDO H_TMS H_D#28 D[27]# D[59]# H_D#60
W5 A[28]# TMS AB5 R24 D[28]# D[60]# AC22
H_A#29 Y4 AB6 H_TRST# H_D#29 L25 AD23 H_D#61
H_A#30 A[29]# TRST# H_D#30 D[29]# D[61]# H_D#62
U2 A[30]# DBR# C20 T25 D[30]# D[62]# AF22
H_A#31 V4 R0302 R0304 H_D#31 N25 AC23 H_D#63
H_A#32 A[31]# 1KOhm 1KOhm D[31]# D[63]#
W3 A[32]# 10 H_DSTBN#1 L26 DSTBN[1]# DSTBN[3]# AE25 H_DSTBN#3 10
H_A#33 AA4 THERMAL 1% 10 H_DSTBP#1 M26 AF24 H_DSTBP#3 10
H_A#34 A[33]# DSTBP[1]# DSTBP[3]#
AB2 A[34]# 10 H_DINV#1 N24 DINV[1]# DINV[3]# AC20 H_DINV#3 10
H_A#35 AA3 D21 H_PROCHOT_S#
A[35]# PROCHOT# GTL_REF H_COMP0
10 H_ADSTB#1 V1 ADSTB[1]# THRMDA A24 CPU_THRM_DA 50 AD26 GTLREF COMP[0] R26
B25 CPU_THRM_DC 50 CPU_T1 C23 MISC U26 H_COMP1
THRMDC CPU_T2 TEST1 COMP[1] H_COMP2
20 H_A20M# A6 A20M# D25 TEST2 COMP[2] AA1
A5 C7 R0305 T0305 1 C24 Y1 H_COMP3
20 H_FERR# FERR# THERMTRIP# PM_THRMTRIP# 11,32 TEST3 COMP[3]
20 H_IGNNE# C4 2KOhm AF26
IGNNE# 1% T0306 TEST4
1 AF1 TEST5 DPRSTP# E5 H_DPRSTP# 11,20,80
20 H_STPCLK# D5 STPCLK# A26 TEST6 DPSLP# B5 H_DPSLP# 20
20 H_INTR C6 H CLK 1 T0303 D24 H_DPWR# 10
LINT0 DPWR#
20 H_NMI B4 A22 CLK_CPU_BCLK 29 29 CPU_BSEL0 B22 D6 H_PWRGD 20
LINT1 BCLK[0] BSEL[0] PWRGOOD
20 H_SMI# A3 SMI# BCLK[1] A21 CLK_CPU_BCLK# 29 29 CPU_BSEL1 B23 BSEL[1] SLP# D7 H_CPUSLP# 10
1 29 CPU_BSEL2 C21 AE6 PM_PSI# 80
T0304 BSEL[2] PSI#
M4 RSVD1
N5 SOCKET478B
RSVD2
T2 RSVD3
V3 RSVD4
B2 RSVD5 BCLK FSB BSEL2BSEL1BSEL0
C3 RSVD6
T0301 1 D2 166 667 0 1 1
RSVD7
D22 RSVD8
D3 RSVD9 200 800 0 1 0
T0302 1 F6 RSVD10
B B
Default Strapping When XDP/ITP Not Used CPU Test Pin AGTL+ I/O Buffer Compensation
SOCKET478B
+VCCP R0306 @ R0308
1KOhm 1% 27.4Ohm 1%
H_PREQ# R0312 1 2 54.9Ohm 1% 2 1 CPU_T1 H_COMP0 1 2
H_TDI R0313 1 2 150Ohm 1%
H_TMS R0314 1 2 39Ohm
H_TCK R0315 1 2 27.4Ohm 1%
H_TRST# R0303 1 2 649Ohm 1%
R0307 @ R0309
1KOhm 1% 54.9Ohm 1%
2 1 CPU_T2 H_COMP1 1 2
R0310
27.4Ohm 1%
H_COMP2 1 2
D0301 @
RB751V-40
H_PROCHOT_S# 1 2 PWRLIMIT# 30,88 R0311
54.9Ohm 1%
H_COMP3 1 2
A 3 A
D Q0301
2N7002
11
THRO_CPU 30
G
S 2
Title : CPU_Merom(Host)
ASUSTeK COMPUTER INC. NB1 Engineer: John Hung
Size Project Name Rev
Custom 2.0
Date: Monday, September 03, 2007 Sheet 3 of 95
5 4 3 2 1
5 4 3 2 1
Main Board
U0301D
A4 VSS1 VSS82 P6
A8 VSS2 VSS83 P21
A11 VSS3 VSS84 P24
D A14 VSS4 VSS85 R2 D
A16 VSS5 VSS86 R5
+VCORE +VCORE
Max: 44A A19 VSS6 VSS87 R22
A23 VSS7 VSS88 R25
U0301C AF2 T1
VSS8 VSS89
A7 VCC1 VCC68 AB20 B6 VSS9 VSS90 T4
A9 VCC2 VCC69 AB7 B8 VSS10 VSS91 T23
A10 VCC3 VCC70 AC7 B11 VSS11 VSS92 T26
A12 VCC4 VCC71 AC9 B13 VSS12 VSS93 U3
A13 VCC5 VCC72 AC12 B16 VSS13 VSS94 U6
A15 VCC6 VCC73 AC13 B19 VSS14 VSS95 U21
A17 VCC7 VCC74 AC15 B21 VSS15 VSS96 U24
A18 VCC8 VCC75 AC17 B24 VSS16 VSS97 V2
A20 VCC9 VCC76 AC18 C5 VSS17 VSS98 V5
B7 VCC10 VCC77 AD7 C8 VSS18 VSS99 V22
B9 VCC11 VCC78 AD9 C11 VSS19 VSS100 V25
B10 VCC12 VCC79 AD10 C14 VSS20 VSS101 W1
B12 VCC13 VCC80 AD12 C16 VSS21 VSS102 W4
B14 VCC14 VCC81 AD14 C19 VSS22 VSS103 W23
B15 VCC15 VCC82 AD15 C2 VSS23 VSS104 W26
B17 VCC16 VCC83 AD17 C22 VSS24 VSS105 Y3
B18 VCC17 VCC84 AD18 C25 VSS25 VSS106 Y6
B20 VCC18 VCC85 AE9 D1 VSS26 VSS107 Y21
C9 VCC19 VCC86 AE10 D4 VSS27 VSS108 Y24
C10 VCC20 VCC87 AE12 D8 VSS28 VSS109 AA2
C12 AE13 D11 AA5
VCC21 VCC88 VSS29 VSS110
C13 VCC22 VCC89 AE15 D13 VSS30 VSS111 AA8
C15 VCC23 VCC90 AE17 D16 VSS31 VSS112 AA11
C17 VCC24 VCC91 AE18 D19 VSS32 VSS113 AA14
C18 VCC25 VCC92 AE20 D23 VSS33 VSS114 AA16
C
D9 VCC26 VCC93 AF9 D26 VSS34 VSS115 AA19 C
D10 VCC27 VCC94 AF10 E3 VSS35 VSS116 AA22
D12 VCC28 VCC95 AF12 E6 VSS36 VSS117 AA25
D14 VCC29 VCC96 AF14 E8 VSS37 VSS118 AB1
D15 VCC30 VCC97 AF15 E11 VSS38 VSS119 AB4
D17 VCC31 VCC98 AF17
+VCCP
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