Service Manuals, User Guides, Schematic Diagrams or docs for : benq BENQ_S52_(Quanta_ED2)
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ED2-UMA DESIGN VER : 1C
RUN POWER AC/BATT
A
SW CONNECTOR
PG 37 Dothan DC/DC
A
+3V_SRC CPU VR CLOCKS
(478 Micro-FCPGA) +5VSUS
PG 34
BATT
PG 37 PG 34 PG 33 PG 17
CHARGER
PG 5, 6
FSB
133MHZ
LVDS Panel Connector
DDR-SODIMM1 Alviso 915GM/GML PG 18
PG 15, 16 333 MHZ DDR I S-Video
TVOUT S-Video reserved
1257 PCBGA PG 24
DDR-SODIMM2
VGA VGA PR-VGA
PG 15, 16
B
PG 7,8,9,10, 11 PG 19 B
DMI USB2.0 (P3) Bluetooth
USB2.0
interface PG 24
SATA - HDD (P0~P7) USB2.0 (P2) PR-USB2.0
SATA0
PG 20 USB2.0 (P0~P1,P4) USB2.0 I/O P2 reserved for
third USB
Ports PG 24
PATA - HDD ICH6-M
PATA 100 LAN Magnetics RJ45
PG 26 PG 26
PG 20 RTL8100S Port
PR-LAN
PG 25 Replicator
609 BGA
Internal ODD PCI Bus 33MHz
CD-ROM
PG 31
PG 20 PG 12,13, 14
AC97/Azalia MINI-PCI
C
CARDBUS PC7411 C
PG 21,22,23 PG 24
Conexant Audio LPC
PCMCIA Card IEEE1394 Wireless
PG 28 CON. Reader CONN. LAN Card
PG 21 PG 22 PG 23 PG 24
Serial PR-COM
AUDIO MDC DAA KBC
NS97551 Super IO
Amplifier
Parallel PR-Printer
PG 29 PG 30 PG 32
LPC47N217
X-Bus
PR-PS/2
Jack to Audio MODEM Key Touch Flash PR-Audio out
D
Speaker Jacks RJ 11 Matrix Pad PG 31 IrDA D
PG 29 PG 29 PG 26 PG 27 PG 27 PG 32 PG 31
PROJECT : ED2
Quanta Computer Inc.
Size Document Number R ev
Block Diagram 1 C2A
Date: Friday, October 22, 2004 Sheet 1 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
PCI ROUTING
TABLE IDSEL INTERUPT DEVICE SMB I
REQ0# / GNT0# AD24 PIRQA# RTL8110S
A CLK A
REQ2# / GNT2# AD19 PIRQB# , PIRQD# MINI-PCI
REQ1# / GNT1# AD17 PIRQC#,PIRQD#,PIRQA# TI 7411
GEN
MOSFET
ICH6
DIMM1
DIMM0
+3VSUS +3VRUN
SMB II
B B
MOSFET
NS551
551 Smart Thermal
EPROM Battery IC of
CPU
+3VALW +3VRUN
C C
D D
PROJECT : ED2
Quanta Computer Inc.
Size Document Number Rev
Block Diagram 2 C2A
Date: Friday, October 22, 2004 Sheet 2 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
A A
VIN VHCORE DC_IN FB VA Diode AO4404
SC451
HWPG
VRON
IMVP_PWRGD
CPU_VID[0..5] LM339 VIN +15VALW MAIND +12VRUN
AO4411 2N7002
Charger MAX1632A
STP_CPU# +12VALW
DPRSLPVR
CLK_EN#
AOD4411
PSI +5VALW +5VSUS
AO4812
MAIND
Battery MBATT FB +5VRUN
3.3VREF SUSD
VIN +VCCP
+3VALW +3VSUS
MAINON LM27281 +2_5VSUS AO4812
AO4414 MAIND
B +2_5VRUN PG HWPG +3VRUN B
SUSON HWPG SUSD
MAIND
+3V_S5
SI5402
S5_ON
VIN HWPG +1_5VRUN
AO4414
SC1470
SUSON +1_5VSUS
+3VRUN FB FB AVDD_CLK
Pass Through AIC1117 AMCVDD FB +3_3VDC
+2_5VSUS for SUS Rail
+1_25VSUS
G2966
+5VRUN FB AVDD FB +3_3VDD
MAINON Controlled
for RUN Rail
+2_5VRUN +1_25VRUN
+3VSUS FB +3V_MODEM
C C
+5VRUN AO6402 FAN_PWR
+5VRUN FB +5VHDD +3V_LAN_D 1197 +2P5V_LAN FB DVDD_LAN
+3V_S5 FB
CTRL25
+5VRUN FB +5VODD FB
+3V_LAN_A
+3VRUN FB +3VHDD
1197
CTRL18 +1P8V_LAN
D D
PROJECT : ED2
Quanta Computer Inc.
Size Document Number Rev
Block Diagram 3 C2A
Date: Friday, October 22, 2004 Sheet 3 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
INDEX Power and Ground
Pg# Description DNI LIST New Label NOTE Description Control Signal or Source
VA AC ADAPTER (20V)
1-3 Schematic Block Diagram
VIN MAIN POWER (10~20V)
4 FRONTPAGE
MBATT MAIN BATTERY + (10~17V)
5-6 Dothan/Younah
+15VALW +15V ALWAYS
7-11 ALVISO GM
+12VALW +12V ALWAYS
A 12-14 ICH6M A
+12VRUN +12V RUN MAINON
15-16 DDRI SO-DIMM(200P)
17 CLOCK GENERATOR
+5VALW +5V ALWAYS & KBC POWER
18-19 LCD CONN & CRT CONN
+5V_S5 NO USE THIS POWER WILL BE TUNEED OFF IN S5 BATTERY MODE S5_ON
20 SATA & IDE (HDD&CD_ROM)
+5VSUS +5V S5 CONTROLED POWER SUSD
21-23 PCI7411 & CONN & IEEE1394
+5VRUN +5V S3 CONTROLED POWER MAIND
24 MINI-PCI & MDC CONN
+5VHDD CONNECT TO +5VRUN DIRECTLY +5V HDD POWER +5VHDD_EN#
25-26 LAN & LAN Conn.
+5VODD CONNECT TO +5VRUN DIRECTLY +5V ODD POWER +5VMOD_EN#
27 TOUCH PAD & FAN&KB
+5VFDD NO USE EXTERNAL FDD POWER (5V) +5VFDD_EN#
28 Azilia AC97 CODEC
FAN_PWR FAN POWER (5V) VFAN, MAX6657_OV#
29 Audio Amplifier
VDDA Amplifier Power 5V RUN Plane +5VRUN
30 MODEM
AMCVDD AC97 Code DAC Power 3VRUN +3VSUS
31 DOCKING & SIO & FIR
3V_MODEM MODEM Power 3VSUS +5VRUN or +3VRUN
32 KBC PC97551
33 CPU Power
B +3VALW 8051 POWER (3V) B
34 3.3V/5V/12V/15V
+3V_S5 THIS POWER WILL BE TUNEED OFF IN S5 BATTERY MODE S5_ON
35 1.5VSUS/1.5VRUN
+3VSUS SLP_S5# CTRLD POWER SUSD
36 +VCCP/+1.25V/+2.5V
+3VRUN SLP_S3# CTRLD POWER MAIND
37 Battery & Charger
+3VHDD CONNECT TO +3VRUN DIRECTLY SATA HDD Power +3VHDD_EN#
+3V_LAN_D LAN Digital Power +3V_S5
+3V_LAN_A LAN Analog Power +3V_S5
+2P5V_LAN LAN Analog Power +3V_LAN_D (+3V_S5)
DVDD_LAN LAN Digital Power 1.8 or 2.5V +2P5V_LAN(+3V_S5)
RTCVCC RTC & PCL POWER
REF3V
+2_5VSUS SUSON
+2_5VRUN MAIND
C +1_8VSUS NO USE C
+1_8VRUN NO USE +2_5VRUN
+1_8V_M24 NO USE +1_8VSUS or +1_8VRUN
+1_5V_S5 THIS POWER WILL BE TUNEED OFF IN S5 BATTERY MODE S5_ON
+1_5VSUS SUSON
+1_5VRUN AGP I/O POWER MAIND
+1_25VSUS SMDDR_VTERM +2_5VSUS
+1_25VRUN MAINON
VGA1_2V NO USE ATI VGA 1.2V +2_5VRUN
VGACORE NO USE ATI VGA CORE 1.0/1.2V MAINON, POW_SW
+VCCP AGTL+ POWER (1.05V) MAINON
VHCORE CPU CORE POWER (1.25/1.15V) VR_ON, HWPG
GND ALL PAGES DIGITAL GROUND
AGND Page 28,29 AUDIO GND
D D
GNDP NO USE CPU POWER GND
CGNDP NO USE CHARGER GND
DC_GND DC Jcak DC/DC POWER GND
PROJECT : ED2
LANGND NO USE COMBO CONN GND Quanta Computer Inc.
Size Document Number Rev
Index C2A
Date: Friday, October 22, 2004 Sheet 4 of 38
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
CT_0505: Change footprint to +3VRUN +3VRUN
BGA479M-SOCKET from
L100505 from MPGA479M
HD#[0..63]
U31A HD#[0..63] 7
R69
HA#[3..31] 10K-0402 Q14
7 HA#[3..31]
2
HA#3 P4 A19 HD#0 2N7002
HA#4 A3# D0# HD#1
U4 A25
HA#5
HA#6
V3
A4#
A5#
Dothan D1#
D2# A22 HD#2
HD#3
1 3 MBDATA MBDATA 32,37
R3 A6# D3# B21
HA#7 V2 A24 HD#4
HA#8 A7# D4# HD#5
A
HA#9
W1
T4
A8# 1 OF 3 D5# B26
A21 HD#6 +3VRUN +3VRUN A
HA#10 A9# D6# HD#7
W2 A10# D7# B20
HA#11 Y4 C20 HD#8
HA#12 A11# D8# HD#9 +3VRUN R66
Y1 B24
HA#13 U1
A12#
A13#
D9#
D10# D24 HD#10 15 MIL Item9
HA#14 AA3 E24 HD#11 R68 47 3V_THM 10K-0402
HA#15 A14# D11# HD#12 Q13
Y3 A15# D12# C26
2
HA#16 AA2 B23 HD#13 C83 2N7002
HA#17 A16# D13# HD#14
AF4 A17# D14# E23
HA#18 AC4 C25 HD#15 .1U/10V_4 1 3 MBCLK MBCLK 32,37
HA#19 A18# D15# HD#16
AC7 A19# D16# H23
HA#20 HD#17 U18
AC3 A20# D17# G25
HA#21 AD3 L23 HD#18 1 7 KBSMDAT 0 1 2 R71
A21# D18# VCC SMDATA THRM# 13
HA#22 AE4 M26 HD#19 THERMDC 3 8 KBSMCLK
HA#23 A22# D19# HD#20 DXN SMCLK
AD2 A23# D20# H24 2 DXP -ALT 6 MAX6657_AL# 32
HA#24 AB4 F25 HD#21 4 5
HA#25 A24# REQUEST DATA D21# HD#22 -OVT GND
AC6 A25# D22# G24
HA#26 AD5 PHASE PHASE J23 HD#23 10 mil trace / MAX6657 +3VRUN R72
HA#27 A26# D23# HD#24 C86 10K-0402
AE2 SIGNALS SIGNALS M23
HA#28 AD6
A27# D24#
J25 HD#25 10 mil space
HA#29 A28# D25# HD#26 2200P
AF3 A29# D26# L26
HA#30 AE1 N24 HD#27 R310
HA#31 A30# D27# HD#28 10K-0402
AF1 A31# D28# M25
H26 HD#29 +3VRUN
D29# HD#30 THERMDA
D30# N25 MAX6657_OV# 27,34
K25 HD#31
D31# HD#32
7 HADSTB0# U3 ADSTB0# D32# Y26
AE5 AA24 HD#33
7 HADSTB1# ADSTB1# D33#
T25 HD#34
D34# HD#35
B
D35# U23 B
R2 V23 HD#36
7 HREQ#0 REQ0# D36#
P3 R24 HD#37
7 HREQ#1 REQ1# D37#
T2 R26 HD#38
7 HREQ#2 REQ2# D38#
P1 R23 HD#39
7 HREQ#3 REQ3# D39#
T1 AA23 HD#40
7 HREQ#4 REQ4# D40#
U26 HD#41
D41# HD#42
D42# V24
ERROR HD#43
7 ADS# N2 ADS# SIGNALS D43# U25
V26 HD#44
ITP disable guidelines
D44# HD#45
D45# Y23 Signal Resistor Value Connect To Resistor Placement
AA26 HD#46
IERR# D46# HD#47
A4 IERR# D47# Y25 TDI 150 ohm +/- 5% VTT Within 2.0" of the CPU
AB25 HD#48
D48# HD#49
7 HBREQ0# N4 BREQ0# D49# AC23 TMS 39 ohm +/- 5% VTT Within 2.0" of the CPU
J3 ARBITRATION AB24 HD#50
7 BPRI# BPRI# D50#
L1 PHASE AC20 HD#51 TRST# 680 ohm +/- 5% GND Within 2.0" of the CPU
7 BNR# BNR# D51#
J2 SIGNALS AC22 HD#52
7 HLOCK# LOCK# D52#
AC25 HD#53 TCK 27 ohm +/- 5% GND Within 2.0" of the CPU
D53# HD#54
7 HIT# K3 HIT# D54# AD23
K4 SNOOP PHASE AE22 HD#55 TDO Open VTT Within 2.0" of the CPU
7 HITM# HITM# D55#
L4 SIGNALS AF23 HD#56
7 DEFER# DEFER# D56#
AD24 HD#57 Note: Populate R58, R62 when ITP
BPM0# D57# HD#58
C8 AF20
BPM1# B8
BPM0# RESPONSE D58#
AE21 HD#59 connector is populated.
BPM2# BPM1# PHASE D59# HD#60
A9 BPM2# D60# AD21
BPM3# C9 SIGNALS AF25 HD#61
BPM3# D61# HD#62 +VCCP +3VSUS
7 HTRDY# M3 TRDY# D62# AF22
H1 AF26 HD#63
7 RS#0 RS0# D63#
K1 R60 56_4
C 7 RS#1 RS1# C
L2 FERR# 1 2
7 RS#2 RS2#
1
A20M# C2 C23 R319 56_4 R318
12 A20M# A20M# DSTBN0# HDSTBN0# 7
FERR# D3 PC C22 IERR# 1 2 150/F_4
12 FERR# FERR# DSTBP0# HDSTBP0# 7
IGNNE# A3 COMPATIBILITY K24
12 IGNNE# IGNNE# DSTBN1# HDSTBN1# 7
CPUPWRGD E4 SIGNALS L24 R58 200/F
12 CPUPWRGD HDSTBP1# 7
2
SMI# PWRGOOD DSTBP1# CPUPWRGD
12 SMI# B4 SMI# DSTBN2# W25 HDSTBN2# 7 1 2
W24 DBR#
DSTBP2# HDSTBP2# 7
TCK A13 AE24
TCK DSTBN3# HDSTBN3# 7
TDO A12 DIAGNOSTIC AE25
TDO DSTBP3# HDSTBP3# 7
TDI C12 & TEST
TMS TDI
C11 SIGNALS
TRST# TMS
B13 TRST# DINV0# D25 HDBI0# 7
T91 *PAD A16 J26 +VCCP +VCCP
ITP_CLK0 DINV1# HDBI1# 7
T93 *PAD A15 T24 R315 27.4/F
ITP_CLK1 DINV2# HDBI2# 7
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