Service Manuals, User Guides, Schematic Diagrams or docs for : benq BenQ_Joybook_U102_COMPAL_LA-5241P_KTV00-REV_1.0
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A B C D E
ZZZ1
PCB
1 1
PJP1
45@ DCIN
2
Compal Confidential 2
KTV00 Schematics Document
Intel Diamondville Processor with Calistoga(945GSE) + DDRII + ICH7M
3 3
2009-05-07
REV: 1.0
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KTV00 LA-5241P
Date: Thursday, May 07, 2009 Sheet 1 of 39
A B C D E
A B C D E
Compal Confidential Diamondville SC
FCBGA8
Model Name : KTV00 437Pins
File Name : LA-5241P 22x22mm
page 4,5
1
FSB Clock Generator 1
CRT Conn H_A#(3..31) 400/533MHz H_D#(0..63) CK505 page 12
page 14
RGB
Calistoga GSE Memory BUS(DDRII) DDRII-SO-DIMM
page 11
FCBGA998
1.8V DDRII 400/533
LCD Conn. LVDS
Thermal Sensor page 13 27x27mm
EMC1402 page 6,7,8,9,10
page 2
DMI USB Port X1
page 28
X2 mode
USB USB Board X2
PCI-Express ICH7M HDA page 28
BGA652 USB Card
2 Reader X1 2
31x31mm RTS5159E
page 23
page 15,16,17,18
MINI Card x1 10/100 Ethernet SATA CMOS CAM
RTL 8103EL page22
SATA HDD CONN
page 19 page 24
page 22 WLAN Card
page19
LPC BUS
Transformer 3G Card
page19
page 24
HDA Codec Blue tooth
ALC272 page19
page 20
Power ON/OFF RJ45
DC/DC Interface
page 29 page 24
& LED & LID
page 26
3
3VALW/5VALW ENE KBC 3
page 34
SPI
DC IN KB926 rev.D3
page 31 page 25
1.05VP/1.8VP
page 35 AMP & INT INT MIC HeadPhone &
BATT IN MIC Jack
page 32 Speaker 21
page
page 20
page 21
2.5VSP/0.9VSP/1.5VSP Int.KBD SPI ROM
page 27 page 25
CHARGER page 36 Touch Pad
page 33
page 27
CPU_CORE
page 37
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KTV00 LA-5241P
Date: Thursday, May 07, 2009 Sheet 2 of 39
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1 1
Voltage Rails
External PCI Devices
Power Plane Description S1 S3 S5
VIN Adapter power supply (19V) N/A N/A N/A
DEVICE IDSEL # REQ/GNT # PIRQ
B+ AC or battery power rail for power circuit. N/A N/A N/A
No PCI Device
+CPU_CORE Core voltage for CPU ON OFF OFF
+0.9VS 0.9V switched power rail for DDR terminator ON OFF OFF
+VCCP VCCP switched power rail ON OFF OFF
+1.5VS 1.5V switched power rail ON OFF OFF
+1.8V 1.8V power rail for DDR ON ON OFF
+2.5VS 2.5V switched power rail ON OFF OFF
+3VALW 3.3V always on power rail ON ON ON*
+3VS 3.3V switched power rail ON OFF OFF
2 2
+5VALW 5V always on power rail ON ON ON*
+5VS 5V switched power rail ON OFF OFF
+VSB VSB always on power rail ON ON ON*
+RTCVCC RTC power ON ON ON
EC SM Bus1 address EC SM Bus2 address
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
Device Address Device Address
Smart Battery 0001 011X b EMC1402 1001 100X b
SIGNAL
STATE SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Full ON HIGH HIGH HIGH ON ON ON ON
S1(Power On Suspend) HIGH HIGH HIGH ON ON ON LOW
S3 (Suspend to RAM) LOW HIGH HIGH ON ON OFF OFF
3 3
S4 (Suspend to Disk) LOW LOW HIGH ON OFF OFF OFF
S5 (Soft OFF) LOW LOW LOW ON OFF OFF OFF
ICH7M SM Bus address
BOARD ID Table(Page 25) Device Address
ID BRD ID Ra Rb Vab Clock Generator 1101 001Xb
(SLG8SP556VTR)
0 R01 (EVT) NC 0 0V DDR DIMMA 1010 000Xb
1 R02 (DVT) 100K 8.2K 0.25V
2 R03 (PVT) 100K 18K 0.50V
3 R10A (MP) 100K NC 3.3V
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2006/08/18 Deciphered Date 2008/09/20 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
KTV00 LA-5241P
Date: Thursday, May 07, 2009 Sheet 3 of 39
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5 4 3 2 1
<6> H_A#[3..16]
U19A U19 <6> H_D#[0..15] U19B H_D#[32..47] <6>
H_A#3 P21 V19 H_ADS# +VCCP +VCCP H_D#0 Y11 R3 H_D#32
H_A#4 A[3]# ADS# H_BNR# H_ADS# <6> H_D#1 D[0]# D[32]# H_D#33
H20 A[4]# BNR# Y19 H_BNR# <6> W10 D[1]# D[33]# R2
H_A#5 N20 U21 H_BPRI# H_D#2 Y12 P1 H_D#34
A[5]# BPRI# H_BPRI# <6> D[2]# D[34]#
1
1
H_A#6 R20 H_D#3 AA14 N1 H_D#35
A[6]# D[3]# D[35]#
0
GROUP
ADDR
DATA GRP 0
DATA GRP 0
H_A#7 J19 T21 H_DEFER# R31 R50 H_D#4 AA11 M2 H_D#36
A[7]# DEFER# H_DEFER# <6> D[4]# D[36]#
H_A#8 N19 T19 H_DRDY# 56_0402_5% 330_0402_5% AU80586GF028512 _FCBGA437 H_D#5 W12 P2 H_D#37
H_A#9 A[8]# DRDY# H_DBSY# H_DRDY# <6> N280@ H_D#6 D[5]# D[37]# H_D#38
G20 A[9]# DBSY# Y18 H_DBSY# <6> AA16 D[6]# D[38]# J3
H_A#10 M19 H_D#7 Y10 N3 H_D#39
DATA GRP 2
2
2
H_A#11 A[10]# H_BR0# H_D#8 D[7]# D[39]# H_D#40
H21 A[11]# BR0# T20 H_BR0# <6> Y9 D[8]# D[40]# G3
H_A#12 L20 H_D#9 Y13 H2 H_D#41
A[12]# D[9]# D[41]#
CONTROL
H_A#13 M20 F16 H_IERR# H_D#10 W15 N2 H_D#42
H_A#14 A[13]# IERR# H_INIT#_R R51 1 D[10]# D[42]#
K19 A[14]# INIT# V16 2 1K_0402_5% H_INIT# <16>
H_D#11 AA13 D[11]# D[43]# L2 H_D#43
D H_A#15 H_D#12 H_D#44 D
J20 A[15]# Y16 D[12]# D[44]# M3
H_A#16 L21 W20 H_LOCK# Close to CPU H_D#13 W13 J2 H_D#45
A[16]# LOCK# H_LOCK# <6> D[13]# D[45]#
H_ADSTB#0 K20 H_D#14 AA9 H1 H_D#46
<6> H_ADSTB#0 @ T4 H_AP0 ADSTB[0]# H_RESET# H_D#15 D[14]# D[46]# H_D#47
<6> H_REQ#[0..4] D17 AP0 RESET# D15 H_RESET# <6> H_RS#[0..2] <6> W9 D[15]# D[47]# J1
PAD H_REQ#0 N21 W18 H_RS#0 H_DSTBN#0 Y14 K2 H_DSTBN#2
H_REQ#1 REQ[0]# RS[0]# H_RS#1 <6> H_DSTBN#0 H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 H_DSTBN#2 <6>
J21 REQ[1]# RS[1]# Y17 <6> H_DSTBP#0 Y15 DSTBP[0]# DSTBP[2]# K3 H_DSTBP#2 <6>
H_REQ#2 G19 U20 H_RS#2 H_DINV#0 W16 L1 H_DINV#2
H_REQ#3 REQ[2]# RS[2]# H_TRDY# <6> H_DINV#0 @ H_DP#0 DINV[0]# DINV[2]# H_DP#2 @ H_DINV#2 <6>
P20 REQ[3]# TRDY# W19 H_TRDY# <6> V9 DP#0 DP#2 M4
H_REQ#4 R19 T5 PAD PAD T8
REQ[4]# H_HIT# <6> H_D#[16..31] H_D#16 H_D#48 H_D#[48..63] <6>
<6> H_A#[17..31] HIT# AA17 H_HIT# <6> AA5 D[16]# D[48]# C2
H_A#17 C19 V20 H_HITM# H_D#17 Y8 G2 H_D#49
H_A#18 A[17]# HITM# H_HITM# <6> H_D#18 D[17]# D[49]# H_D#50
F19 A[18]# W3 D[18]# D[50]# F1
H_A#19 E21 K17 H_D#19 U1 D3 H_D#51
H_A#20 A[19]# BPM[0]# H_D#20 D[19]# D[51]# H_D#52
A16 A[20]# BPM[1]# J18 W7 D[20]# D[52]# B4
DATA GRP 1
DATA GRP 1
H_A#21 D19 H15 H_D#21 W6 E1 H_D#53
H_A#22 A[21]# BPM[2]# H_D#22 D[21]# D[53]# H_D#54
C14 A[22]# BPM[3]# J15 Y7 D[22]# D[54]# A5
ADDR GROUP 1
ADDR GROUP 1
H_A#23 C18 K18 H_D#23 AA6 C3 H_D#55
H_A#24 A[23]# PRDY# PREQ# H_D#24 D[23]# D[55]# H_D#56
DATA GRP 3
C20 A[24]# PREQ# J16 Y3 D[24]# D[56]# A6
XDP/ITP SIGNALS
H_A#25 E20 M17 ITP_TCK H_D#25 W2 F2 H_D#57
H_A#26 A[25]# TCK ITP_TDI H_D#26 D[25]# D[57]# H_D#58
D20 A[26]# TDI N16 V3 D[26]# D[58]# C6
H_A#27 B18 M16 ITP_TDO H_D#27 U2 B6 H_D#59
H_A#28 A[27]# TDO ITP_TMS H_D#28 D[27]# D[59]# H_D#60
C15 A[28]# TMS L17 T3 D[28]# D[60]# B3
H_A#29 B16 K16 ITP_TRST# H_D#29 AA8 C4 H_D#61
H_A#30 A[29]# TRST# H_D#30 D[29]# D[61]# H_D#62
B17 A[30]# BR1# V15 V2 D[30]# D[62]# C7
H_A#31 C16 H_D#31 W4 D2 H_D#63
H_A#32 A[31]# H_PROCHOT#_R H_DSTBN#1 D[31]# D[63]# H_DSTBN#3
A17 A[32]# PROCHOT# G17 1 2 VR_TT# <37> <6> H_DSTBN#1 Y4 DSTBN[1]# DSTBN[3]# E2 H_DSTBN#3 <6>
H_A#33 B14 E4 H_THERMDA R314 22_0402_5% H_DSTBP#1 Y5 F3 H_DSTBP#3
THERM
H_A#34 A[33]# THRMDA H_THERMDC <6> H_DSTBP#1 H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 H_DSTBP#3 <6>
B15 A[34]# THRMDC E5 Close to CPU <6> H_DINV#1 Y6 DINV[1]# DINV[3]# C5 H_DINV#3 <6>
H_A#35 A14 H_DP#1 R4 D4 H_DP#3 @
H_ADSTB#1 A[35]# H_THERMTRIP# @ T7 PAD DP#1 DP#3 PAD T6
<6> H_ADSTB#1 B19 ADSTB[1]# THERMTRIP# H17 H_THERMTRIP# <6,16>
H_AP1 M18 +CPU_GTLREF A7 T1 COMP0 1 R46 2 27.4_0402_1%
@ T3 PAD AP1 R47 @ GTLREF COMP[0]
1 2 1K_0402_5% ACLKPH U5 ACLKPH COMP[1] T2 COMP1 1 R45 2 54.9_0402_1%
C H_A20M# R48 @ DCLKPH COMP2 C
<16> H_A20M# U18 A20M# 1 2 1K_0402_5% V5 DCLKPH COMP[2] F20 2 R13 1 27.4_0402_1%
H_FERR# T16 V11 CLK_CPU_BCLK T17 F21 COMP3 2 R5 1 54.9_0402_1%
<16> H_FERR# FERR# BCLK[0] CLK_CPU_BCLK <12> BINIT# COMP[3]
H_IGNNE# J4 V12 CLK_CPU_BCLK# R6 MISC
<16> H_IGNNE# IGNNE# BCLK[1] CLK_CPU_BCLK# <12> EDM
H_STPCLK# R16 +CPU_EXTBGREF M6 R18 H_DPRSTP#
<16> H_STPCLK# STPCLK# EXTBGREF DPRSTP# H_DPRSTP# <16,37>
H_INTR T15 N15 R17 H_DPSLP#
<16> H_INTR LINT0 H_DPSLP# <16>
H CLK
H_NMI FORCEPR# DPSLP# H_DPWR#
<16> H_NMI R15 LINT1 N6 HFPLL DPWR# U4 H_DPWR# <6>
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