Service Manuals, User Guides, Schematic Diagrams or docs for : benq benq_R31E_Quanta_ED5
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PCB P/N AND DESCRIPTION SATA PATA
ED5 SATA ASSY P/N ED5 ASSY P/N VCC_CORE CPU VR
ED5
PCB ED5 MB(8L,309X218, REVA) PCB ED5 USB/B(8L, 47.5X16.8, REVA) ED5 MB S/S ASSY P/N: 51ED5SS0018 ED5 MB S/S ASSY P/N: 51ED5SS0000
P/N: DA0ED5MB8A8 P/N: DA0ED5SB8A5 ED5 MB C/S ASSY P/N: 41ED5CS0015 ED5 MB C/S ASSY P/N: 41ED5CS0007
ED5 MB ASSY P/N: 31ED5MB0012 ED5 MB ASSY P/N: 31ED5MB0004
PG 30
PCB ED5 MB(8L,309X218,REVB)
P/N: DA0ED5MB8B6 PCB ED5 USB/B(8L,47.5X16.8,REVB) W/O ANT ANT +1.2V
ED5 USB/B S/S ASSY P/N: 4NED5SS0011 ED5 USB/B S/S ASSY P/N: 4NED5SS0002
P/N: DA0ED5SB8B3
ED5 USB/B ASSY P/N: 3NED5UB0011 ED5 USB/B ASSY P/N: 3NED5UB0003
+1.2V
+VCCP +VCCP
PG 31
A A
HOST 133/166MHz +1.8VSUS
AMD S1 PCIE 100MHz
+1.8VSUS
CLOCK GENERATOR +1.8V SMDDR
DDRII-SODIMM1 Turion 64 Rev.F Dual-Core/ VGA 96MHz VTERM
ICS951462 SMDDR_VTERM
PG 7,8 533/ 667 MHZ DDR II Sempron Rev.F Single-Core USB 48MHz
PG 32
REF 14MHz
Dual-Core 35W / Single-Core 25W
+3VPCU
DDRII-SODIMM2 (638 S1g1 socket) PG 13 3V/5V
+3V_S5
PG 7,8 PG 3,4,5,6
+3VSUS
HT_LINK +5VSUS
PCI-E, 1X +5V
Express Card
+12V
PCIE1 & USB4 NEW CARD PG 24 PG 33
Panel Connector LVDS
PG 20 PG 19 PCI-E, 1X VIN
RS485 Mini PCI-E Card (WLAN) CHARGER
B
S-Video TVOUT PCIE2 PCI Express Mini Card PG 19 B
PG 34
PG 20 465 FCBGA PCI-E, 1X
Mini PCI-E Card (TV) WIRE
VGA VGA PCI Express Mini Card
PCIE3 &
PG 19
PG 20 PCI-E, 1X
USB5
PG 9,10,11,12 LAN Magnetics RJ45
A_LINK
RTL8111B-GR
SATA - HDD PCIE0 PG 23
SATA0
PG 21
SB460 USB2.0 (P0~P7)
Bluetooth ANTENNA JACK
PATA - HDD
PATA 100 USB7
PG 22
PG 21 B/B CN.
USB2 &
549 BGA USB3 PG 22
USB2.0 I/O Ports USB2.0 I/O
C C
Internal ODD USB0 &
USB1
PG 22
CD-ROM
PG 21 DSC USB I/F USB DAUGHTERBOARD
Azalia USB6 PG 22
PCI Bus 33MHz
PG 14,15,16,17 TI PCI8402 MINI PCI CN.
Azalia Audio AD17 AD20
LPC REQ3#, GNT3# REQ2#, GNT2#
PG 26
INTE#, INTG#, INTH# INTF#, INTG#
KBC PG 24,25 DEBUG PURPOSE ONLY PG 18
Amplifier Azalia MDC NS97551 SWITCH
MAX9755A LED Card Reader IEEE1394 CN.
PG 27 PG 26 PG 28
D
PG 29 D
X-Bus PG 25 PG 25
INT. MODEM K/B Touch Flash
MIC. S.P. H.P RJ 11 CONN. Pad ROM PROJECT : ED5
PG 27 PG 27 PG 27 PG 23 PG 29 PG 29 PG 28 Quanta Computer Inc.
Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Monday, April 10, 2006 Sheet 1 of 34
1 2 3 4 5 6 7 8
5 4 3 2 1
TABLE OF CONTENTS
POWER VOLTAGE ACTIVE SCOPE ROUTING PAGE
Page 01 : BLOCK DIAGRAM
+12V +12V OFF IN S3-S5 PLANE 41
Page 02 : TABLE OF CONTENTS
-12V -12V OFF IN S3-S5 TRACE 20 MIL 41
Page 03 : ATHLON64 HT I/F
+5V +5V OFF IN S3-S5 PLANE 41
Page 04 : ATHLON64 DDRII MEMORY
I/F
Page 05 : ATHLON64 CTRL & DEBUG +3.3V +3.3V OFF IN S3-S5 PLANE 41
SYSTEM
D D
+5VALW +5V S0-S5 PLANE/ 50 MIL 41
Page 06 : ATHLON64 PWR & GND
+3.3VALW +3.3V S0-S5 TRACE 30 MIL 41
Page 07 : DDRII SODIMMX2
+1.8VALW +2.5V S0-S5 TRACE 30 MIL 21
Page 08 : DDRII TERMINATION
+5V_DUAL +5V S0-S5 PLANE/ 100 MIL 41
Page 09 : RS485-HT LINK0
I/F
Page 10 : RS485-PCIE LINK I/ F +3.3V_DUAL +3.3V S0-S5 PLANE/ 50 MIL 41
Page 11 : RS485-SYSTEM I/F & C LKGEN
VCCCORE VID[0..6] OFF IN S3-S5 PLANE+COPER 37
Page 12 : RS485-POWER
CPU
VCCP +1.05V OFF IN S3-S5 PLANE+COPER 38
Page 13 : CLOCK GENERATOR
VCCA +1.5V OFF IN S3-S5 TRACE 20 MIL 38
Page 14 : SB460M-PCIE/ PCI/CPU/LPC
Page 15 : SB460M ACPI/GPIO/USB/AC97 VCC_NB +1.2V/1.0V OFF IN S3-S5 PLANE+COPER 39
Page 16 : SB460M HDD/POWER/DECOUP LI VDD_CPU +1.05V OFF IN S3-S5 PLANE+COPER 38
Page 17 : SB460M STRAPS VDD_MEM +1.8V S0-S3 PLANE+COPER 40
Page 18 : MINI P CI VDD18 +1.8V OFF IN S3-S5 TRACE 20 MIL 12
Page 19 : MINI CARD TV & WLAN VDDA18 +1.8V OFF IN S3-S5 COPPER 12
Page 20 : CRT&LVDS&S-VIDE0&DCS
RC485
C
VDDA12 +1.2V OFF IN S3-S5 PLANE+COPPER 12 C
Page 21 : HDD & CDROM , HOLES
NB
AVDD +3.3V OFF IN S3-S5 TRACE 20 MIL 11
Page 22 : USB, BLUETOOTH AVDDQ +1.8V OFF IN S3-S5 TRACE 20 MIL 11
Page 23 : LAN PCI-E RJ45 & RJ11 PLVDD +1.8V OFF IN S3-S5 TRACE 20 MIL 11
Page 24 : PCI8402_1 & NEW CARD LPVDD +1.8V OFF IN S3-S5 TRACE 20 MIL 11
Page 25 : PCI8402_2 (1394/5IN1) LVDDR +1.8V OFF IN S3-S5 TRACE 30 MIL 11
BONEFISH POWER UP SEQUENCE
Page 26 : AUDIO(ALC262) & MDC VDDR3 +3.3V OFF IN S3-S5 TRACE 30 MIL 11 +5VALW
Page 27 : AUDIO(AMP&POWER&HP CON) VTT_DDR +0.9V OFF IN S3-S5 COPPER 40
RSMRST#
Page 28 : PC97551 & FLASH VDD_CLK +3.3V OFF IN S3-S5 COPPER 14
Page 29 : LED & SW & KB & TP & FAN PS_ON, SLP_S3#, SLP_S5#
+3.3V_SB +3.3V OFF IN S3-S5 PLANE 21
Page 30 : CPU CORE MAX8774
+1.8V_SB +1.8V OFF IN S3-S5 PLANE 21 +12V,5V,3.3V
Page 31 : 1.2V/1.5V/2.5V
+3.3VALW_SB +3.3V S0-S5 PLANE 21
Page 32 : 1.8V/DDRII VDRM_PWRGD
+1.8VALW_SB +1.8V S0-S5 PLANE 21
Page 33 : SYSTEM 3V/5V
+1.8V_SUB_PHY +1.8V S0-S5 TRACE 30 MIL 21 VCC_NB_PWRGD
Page 34 : BATTERY CHARGER
AVDD_CK +1.8V OFF IN S3-S5 TRACE 10 MIL 21
B
VRM_PWRGD B
V5_REF +5V OFF IN S3-S5 TRACE 10 MIL 21
CPU-PWR +1.05V OFF IN S3-S5 TRACE 20 MIL 21 NB_PWRGD
SB460 SB
PCIE_PVDD +1.8V OFF IN S3-S5 TRACE 20 MIL 18
SB_PWRGD
PCIE_VDDR +1.8V OFF IN S3-S5 PLANE+COPER 18
+1.8V_ATA +1.8V OFF IN S3-S5 PLANE 20 CPU_PWRGD
PLLVDD_ATA +1.8V OFF IN S3-S5 TRACE 20 MIL 20
PCI_RST#
XTLVDD_ATA +1.8V OFF IN S3-S5 TRACE 20 MIL 20
AVDD_USB_TX +1.8V S0-S5 PLANE+COPER 19 CPU_RST#
AVDD_USB_RX +1.8V S0-S5 PLANE+COPER 19
+3.3V_AVDDC T1 T2 T3
+3.3V S0-S5 TRACE 20 MIL 19
V_BAT +3.0V -- TRACE 10 MIL 18 T1>= 70 ms 1ms < T2 < 10ms
1ms < T3 < 5ms
A A
PROJECT : ED5
Quanta Computer Inc.
Size Document Number Rev
BLOCK DIAGRAM 1A
Date: Monday, April 10, 2006 Sheet 2 of 34
5 4 3 2 1
5 4 3 2 1
D D
PROCESSOR HYPERTRANSPORT INTERFACE
VLDT_Ax AND VLDT_Bx ARE CONNECTED TO THE LDT_RUN POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VLDT_RUN U21A
D4 AE5 C118
VLDT_A3 VLDT_B3
D3 VLDT_A2 VLDT_B2 AE4
D2 VLDT_A1 VLDT_B1 AE3
D1 VLDT_A0 VLDT_B0 AE2
4.7U/6.3V_6
N5 L0_CADIN_H15 L0_CADOUT_H15 T4 HT_CADOUT15_P (9)
(9) HT_CADIN15_P
(9) HT_CADIN15_N P5 L0_CADIN_L15 L0_CADOUT_L15 T3 HT_CADOUT15_N (9)
M3 L0_CADIN_H14 L0_CADOUT_H14 V5 HT_CADOUT14_P (9)
(9) HT_CADIN14_P
M4 L0_CADIN_L14 L0_CADOUT_L14 U5 HT_CADOUT14_N (9)
(9) HT_CADIN14_N
L5 L0_CADIN_H13 L0_CADOUT_H13 V4 HT_CADOUT13_P (9)
(9) HT_CADIN13_P +1.2V VLDT_RUN
M5 L0_CADIN_L13 L0_CADOUT_L13 V3 HT_CADOUT13_N (9)
(9) HT_CADIN13_N
C (9) HT_CADIN12_P K3 L0_CADIN_H12 L0_CADOUT_H12 Y5 HT_CADOUT12_P (9) C
K4 L0_CADIN_L12 L0_CADOUT_L12 W5 HT_CADOUT12_N (9)
(9) HT_CADIN12_N L58
H3 L0_CADIN_H11 L0_CADOUT_H11 AB5 HT_CADOUT11_P (9)
(9) HT_CADIN11_P
H4 L0_CADIN_L11 L0_CADOUT_L11 AA5 HT_CADOUT11_N (9)
(9) HT_CADIN11_N
G5 L0_CADIN_H10 L0_CADOUT_H10 AB4 HT_CADOUT10_P (9)
(9) HT_CADIN10_P L57
(9) HT_CADIN10_N H5 L0_CADIN_L10 L0_CADOUT_L10 AB3 HT_CADOUT10_N (9)
F3 AD5 FBJ3216HS800
(9) HT_CADIN9_P L0_CADIN_H9 L0_CADOUT_H9 HT_CADOUT9_P (9)
F4 L0_CADIN_L9 L0_CADOUT_L9 AC5 HT_CADOUT9_N (9)
(9) HT_CADIN9_N
E5 L0_CADIN_H8 L0_CADOUT_H8 AD4 HT_CADOUT8_P (9)
(9) HT_CADIN8_P FBJ3216HS800
F5 L0_CADIN_L8 L0_CADOUT_L8 AD3 HT_CADOUT8_N (9)
(9) HT_CADIN8_N
(9) HT_CADIN7_P N3 L0_CADIN_H7 L0_CADOUT_H7 T1 HT_CADOUT7_P (9)
1
1
N2 R1 80 ohm(4A) C105 C104
(9) HT_CADIN7_N L0_CADIN_L7 L0_CADOUT_L7 HT_CADOUT7_N (9)
L1 U2 C110 C116 C108 C112
(9) HT_CADIN6_P L0_CADIN_H6 L0_CADOUT_H6 HT_CADOUT6_P (9)
M1 U3 4.7U/6.3V_6 4.7U/6.3V_6 .22U/6V_4 .22U/6V_4 10P_4 10P_4
(9) HT_CADIN6_N L0_CADIN_L6 L0_CADOUT_L6 HT_CADOUT6_N (9)
2
2
L3 L0_CADIN_H5 L0_CADOUT_H5 V1 HT_CADOUT5_P (9)
(9) HT_CADIN5_P
(9) HT_CADIN5_N L2 L0_CADIN_L5 L0_CADOUT_L5 U1 HT_CADOUT5_N (9)
J1 L0_CADIN_H4 L0_CADOUT_H4 W2 HT_CADOUT4_P (9)
(9) HT_CADIN4_P
K1 L0_CADIN_L4 L0_CADOUT_L4 W3 HT_CADOUT4_N (9)
(9) HT_CADIN4_N
G1 L0_CADIN_H3 L0_CADOUT_H3 AA2 HT_CADOUT3_P (9)
(9) HT_CADIN3_P
(9) HT_CADIN3_N
H1
G3
L0_CADIN_L3 L0_CADOUT_L3 AA3
AB1
HT_CADOUT3_N (9) LAYOUT: Place bypass cap on topside of board
(9) HT_CADIN2_P L0_CADIN_H2 L0_CADOUT_H2 HT_CADOUT2_P (9)
(9) HT_CADIN2_N
G2 L0_CADIN_L2 L0_CADOUT_L2 AA1 HT_CADOUT2_N (9) NEAR HT POWER PINS THAT ARE NOT CONNECTED DIRECTLY
(9) HT_CADIN1_P
E1 L0_CADIN_H1 L0_CADOUT_H1 AC2 HT_CADOUT1_P (9) TO DOWNSTREAM HT DEVICE, BUT CONNECTED INTERNALLY
(9) HT_CADIN1_N
F1 L0_CADIN_L1 L0_CADOUT_L1 AC3 HT_CADOUT1_N (9) TO OTHER HT POWER PINS
B
(9) HT_CADIN0_P
E3 L0_CADIN_H0 L0_CADOUT_H0 AD1 HT_CADOUT0_P (9) PLACE CLOSE TO VLDT0 POWER PINS B
(9) HT_CADIN0_N E2 L0_CADIN_L0 L0_CADOUT_L0 AC1 HT_CADOUT0_N (9)
J5 L0_CLKIN_H1 L0_CLKOUT_H1 Y4 HT_CLKOUT1_P (9)
(9) HT_CLKIN1_P
K5 L0_CLKIN_L1 L0_CLKOUT_L1 Y3 HT_CLKOUT1_N (9)
(9) HT_CLKIN1_N
J3 L0_CLKIN_H0 L0_CLKOUT_H0 Y1 HT_CLKOUT0_P (9)
VLDT_RUN (9) HT_CLKIN0_P
(9) HT_CLKIN0_N J2 L0_CLKIN_L0 L0_CLKOUT_L0 W1 HT_CLKOUT0_N (9)
R76 49.9/F HT_CTLIN1_P P3 T5 HT_CPU_CTLOUT1_P
L0_CTLIN_H1 L0_CTLOUT_H1 T29
HT_CTLIN1_N P4 R5 HT_CPU_CTLOUT1_N
49.9/F L0_CTLIN_L1 L0_CTLOUT_L1 T30
R80
N1 L0_CTLIN_H0 L0_CTLOUT_H0 R2 HT_CTLOUT0_P (9)
(9) HT_CTLIN0_P
P1 L0_CTLIN_L0 L0_CTLOUT_L0 R3 HT_CTLOUT0_N (9)
(9) HT_CTLIN0_N
Athlon 64 S1
Processor Socket
A A
PROJECT : ED5
Quanta Computer Inc.
Size Document Number Rev
ATHLON64 HT I/F 1A
Date: Monday, April 10, 2006 Sheet 3 of 34
5 4 3 2 1
A B C D E
+1.8VSUS
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWER
SUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
ON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE Processor DDR2 Memory Interface
R140
2K/F
U21C
M_B_DQ63 AD11 AA12 M_A_DQ63
(7) M_B_DQ[0..63] MB_DATA63 MA_DATA63 M_A_DQ[0..63] (7)
CPU_M_VREF M_B_DQ62 AF11 AB12 M_A_DQ62
M_B_DQ61 MB_DATA62 MA_DATA62 M_A_DQ61
AF14 MB_DATA61 MA_DATA61 AA14
4 M_B_DQ60 AE14 AB14 M_A_DQ60 4
M_B_DQ59 MB_DATA60 MA_DATA60 M_A_DQ59
Y11 MB_DATA59 MA_DATA59 W11
C180 C181 R141 M_B_DQ58 AB11 Y12 M_A_DQ58
.1U_4 1000p/50V_4
2K/F M_B_DQ57 MB_DATA58 MA_DATA58 M_A_DQ57
AC12 MB_DATA57 MA_DATA57 AD13
M_B_DQ56 AF13 AB13 M_A_DQ56
M_B_DQ55 MB_DATA56 MA_DATA56 M_A_DQ55
AF15 MB_DATA55 MA_DATA55 AD15
M_B_DQ54 AF16 AB15 M_A_DQ54
+1.8VSUS M_B_DQ53 MB_DATA54 MA_DATA54 M_A_DQ53
AC18 MB_DATA53 MA_DATA53 AB17
+0.9V_VTER M_B_DQ52 AF19 Y17 M_A_DQ52
M_B_DQ51 MB_DATA52 MA_DATA52 M_A_DQ51
AD14 MB_DATA51 MA_DATA51 Y14
2
U21B M_B_DQ50 AC14 W14 M_A_DQ50
R363 M_B_DQ49 MB_DATA50 MA_DATA50 M_A_DQ49
AE18 MB_DATA49 MA_DATA49 W16
39.2F W17 D10 M_B_DQ48 AD18 AD17 M_A_DQ48
MEMVREF VTT1 M_B_DQ47 MB_DATA48 MA_DATA48 M_A_DQ47
VTT2 C10 AD20 MB_DATA47 MA_DATA47 Y18
VTT_SENSE Y10 B10 M_B_DQ46 AC20 AD19 M_A_DQ46
T45 VTT_SENSE VTT3 MB_DATA46 MA_DATA46
M_B_DQ45 M_A_DQ45
1
VTT4 AD10 AF23 MB_DATA45 MA_DATA45 AD21
W10 M_B_DQ44 AF24 AB21 M_A_DQ44
M_ZN VTT5 M_B_DQ43 MB_DATA44 MA_DATA44 M_A_DQ43
AE10 MEMZN VTT6 AC10 AF20 MB_DATA43 MA_DATA43 AB18
M_ZP AF10 AB10 M_B_DQ42 AE20 AA18 M_A_DQ42
MEMZP VTT7 M_B_DQ41 MB_DATA42 MA_DATA42 M_A_DQ41
VTT8 AA10 AD22 MB_DATA41 MA_DATA41 AA20
A10 M_B_DQ40 AC22 Y20 M_A_DQ40
VTT9 MB_DATA40 MA_DATA40
2
M_B_DQ39 AE25 AA22 M_A_DQ39
R365 M_B_DQ38 MB_DATA39 MA_DATA39 M_A_DQ38
(7,8) M_A_CS#3 V19 MA0_CS_L3 MA0_CLK_H2 Y16 M_CLKOUT1 (7) AD26 MB_DATA38 MA_DATA38 Y22
39.2F J22 AA16 M_B_DQ37 AA25 W21 M_A_DQ37
(7,8) M_A_CS#2 MA0_CS_L2 MA0_CLK_L2 M_CLKOUT1# (7) MB_DATA37 MA_DATA37
V22 E16 M_B_DQ36 AA26 W22 M_A_DQ36
(7,8) M_A_CS#1 MA0_CS_L1 MA0_CLK_H1 M_CLKOUT0 (7) MB_DATA36 MA_DATA36
T19 F16 M_B_DQ35 AE24 AA21 M_A_DQ35
(7,8) M_A_CS#0 MA0_CS_L0 MA0_CLK_L1 M_CLKOUT0# (7) MB_DATA35 MA_DATA35
M_B_DQ34 M_A_DQ34
1
AD24 MB_DATA34 MA_DATA34 AB22
Y26 AF18 M_B_DQ33 AA23 AB24 M_A_DQ33
(7,8) M_B_CS#3 MB0_CS_L3 MB0_CLK_H2 M_CLKOUT4 (7) MB_DATA33 MA_DATA33
J24 AF17 M_B_DQ32 AA24 Y24 M_A_DQ32
(7,8) M_B_CS#2 MB0_CS_L2 MB0_CLK_L2 M_CLKOUT4# (7) MB_DATA32 MA_DATA32
W24 A17 M_B_DQ31 G24 H22 M_A_DQ31
(7,8) M_B_CS#1 MB0_CS_L1 MB0_CLK_H1 M_CLKOUT3 (7) MB_DATA31 MA_DATA31
U23 A18 M_B_DQ30 G23 H20 M_A_DQ30
(7,8) M_B_CS#0 MB0_CS_L0 MB0_CLK_L1 M_CLKOUT3# (7) MB_DATA30 MA_DATA30
M_B_DQ29 D26 E22 M_A_DQ29
M_B_DQ28 MB_DATA29 MA_DATA29 M_A_DQ28
PLACE THEM CLOSE TO (7,8) M_CKE3 H26 MB_CKE1 MB0_ODT1 W23 M_ODT3 (7,8) C26 MB_DATA28 MA_DATA28 E21
J23 W26 M_B_DQ27 G26 J19 M_A_DQ27
CPU WITHIN 1" (7,8) M_CKE2 MB_CKE0 MB0_ODT0 M_ODT2 (7,8)
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