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Technical Guide
Colour Television
Z8 Chassis
Circuit Explanations
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CONTENTS
1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. TV Signal, Control and Teletext Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. Horizontal Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6. Vertical Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7. East-West Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8. Memory (EEPROM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9. Colour Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. MSP3415D Audio Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11. AF Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
12. Appendices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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1. Introduction
We at Panasonic realise that the service engineer This Technical Guide contains information for Z8
needs to understand the circuitry inside the TV and for chassis and should be used in conjunction with the
this need, we have produced this Technical Guide. relevant Service Manuals for this chassis.
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2. Block Diagrams
2.1. Control Block Diagram
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2.2. Power Supply and Deflection Block
Diagram
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2.3. Video and Mono Audio
Block Diagram
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2.4. Video and Stereo Audio
Block Diagram
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3. Power Supply
The mains AC voltage used for Z8 is fed via connector The output at pin 3 is smoothed further by capacitor
E2 situated on the E-Board. From the connector E2 C1203, and the 5V standby supply output is fed to the
the mains AC power supply is fed via the main TV EEPROM IC1103, the remote control receiver
On/Off switch S801 and line suppression filter L801 IC1104 and the Q-Link circuit. The 5V standby supply
before being fed to the standby transformer T801. is also fed to IC1201, where the output at pin 3 is
smoothed via C1204, to provide 3.3V standby supply
At the standby transformer T801 the AC supply splits
to the Ultimate One Chip (UOC) IC IC601 pin 61, and
into two paths.
the reset IC IC1102. This 3.3V is also used to bias the
The first path sees the AC supply being fed to the standby relay control transistor Q1204.
normally open contact of the standby relay RL801.
The second path from the bridge rectifier sees the
The second path has the AC supply being fed via the supply voltage being fed via resistor R1202 to the
windings P2/P1 of the standby transformer T801. standby relay RL801 and the relay winding to the
collector of transistor Q1201. Transistor Q1201,
which is controlled by Q1204, is responsible for
switching the TV in and out of standby, under the
3.1. Standby Power Supply Circuit control of the UOC IC IC601 pin 1.
The standby transformer T801 has the AC supply as
The two supplies mentioned allow the circuits to
just mentioned being fed via the primary winding
operate during standby, which is required to process
P2/P1.
the switch ON command from the remote control or
The output of the secondary windings S2/S1 of the
local keys, allowing the TV to be switched out of
standby transformer is fed to the bridge rectifier
standby.
D1201, where the AC voltage is full rectified. Here the
To reduce the load on the standby transformer T801,
supply takes two paths.
a 10V supply is fed from transformer T552 pin 6 via
The first path provides smoothing to the supply via rectifying diode D554, R1209 and D1205, to pin 1 of
capacitor C1201 before being fed to IC1202 pin 1. IC1202.
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3.2. Power Supply Circuit 3.3. Operation
The STR-F6523, IC801 is used in the Z8 power The supply voltage for the main power supply circuit
supply to control and regulate the power supply is fed via the standby relay RL801 to the bridge
operation. This device features over-voltage rectifier D802 where the AC voltage is fully rectified
protection and thermal shutdown. The output stage of and smoothed by capacitor C809.
the IC incorporates a built-in MOSFET switching This smoothed DC voltage of approximately 300V
transistor. then feeds the supply to pin 3 of the switched mode
power supply IC IC801, where the DC voltage is held
at the drain of the internal MOSFET, by its parallel
zener diode.
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3.4. Start Up T802 via L803 and R809. The current at terminal B1
is split into two paths.
A start-up circuit is used to start and stop the
The first path follows the current being fed to the
operations of the control IC IC801 (STR-F6523), by winding B1-B2 and back to pin 4 of IC801 via R811
detecting the voltage appearing at the VIN terminal, and D805. Once the control circuit starts operation,
pin 4. the voltage at the VIN terminal pin 4 of IC801 starts to
decrease. However, the drive winding voltage
At start-up, capacitor C810 is charged via R804, reaches the set value before pin 4 voltage drops to the
which causes the voltage at pin 4 of IC801 to shutdown voltage of 10V. Hence the voltage supply to
increase. Once VIN terminal pin 4 voltage reaches pin 4 is maintained.
approximately 16V, IC801 begins to operate and drive The second path is connected from terminal B1 to P2
the internal power MOSFET, causing current to flow of the FBT. This causes current to flow via the winding
through the drain/source terminals at pins 3 and 2, P2-P1, which provides the +B supply to the FBT T552
and to the winding B1-B2 of switching transformer pin 9.
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3.5. Oscillator and Constant Voltage 3.5.2. From 'ON' to 'OFF'
Control Circuit When the voltage on C1 reaches (approx.) 6.5V, the
The oscillator within IC801 makes use of the charging output from the oscillator is reversed, and the internal
and discharging of internal capacitor C1 (4700pF) switching power MOSFET switches OFF.
and generates pulse signals which turn the internal
power MOSFET On and Off. The constant voltage 3.5.3. 'OFF' Condition and Time
control of a switch mode power supply is performed With the power MOSFET now OFF, Capacitor C1
by fixing the OFF time of the MOSFET (around 50uS) starts discharging through R1, at the fixed time
and changing the ON time in the pulse width control determined by the time constant C1, R1.
operation.
3.5.4. From 'OFF' to 'ON'
3.5.1. 'ON' Condition and Time
When C1 voltage has dropped to around 3.7V, the
When the switching power MOSFET is ON, C1
output from the oscillator is reversed again and the
begins to charge.
power MOSFET again turns ON, thus repeating the
cycle.
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3.6. Regulation 3.7. Drive Circuit
The power supply ON time is changed by controlling The drive circuit charges and discharges the
the the charge current of the internal capacitor C1. capacitance between the gate and the source
D804 is a photocoupler, which provides the drive terminals of the internal power MOSFET, by receiving
current to the 'FB' (Feedback) terminal of IC801 pin pulses from the oscillator. The basic circuit
1 via D812 and R806. The photocoupler current configuration is a totem-pole type connection of
varies in response to the output from pin 2 of transistors. Since the maximum sink current (0.3A)
comparator IC IC802. can become active even when the VIN voltage is lower
IC802 pin 1 monitors the +B supply voltage via the than the shutdown voltage, the drive circuit turns off
zener diode D814 by comparing it with a reference the MOSFET without fail.
voltage established internally within IC802.
If the AC mains input voltage to the switched mode
power supply increases, the +B voltage level tends to
rise. This results in an increased current flow to the FB
terminal, pin 1 of IC801 via the photocoupler D804,
diode D812 and resistor R806. Increasing the rate at
which C1 charges, causes the power MOSFET ON
time to reduce. This in turn causes the +B level to
return to its nominal value.
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3.8. Protection Circuitry
3.8.1. Over-voltage Protection (OVP)
Over-voltage Protection is used to protect IC801 if VIN
pin 4 terminal rises to approximately 22V. Although it 16V
basically functions as protection for pin 4 against
overvoltage, it is also used to protect against
overvoltage of the secondary output (in the event of 10V
failure of the regulation, for example). This is because
pin 4 is supplied by winding B1-B2 of transformer
T802, this voltage being proportional to the output t
voltage of the secondary side.
3.8.2. Over-current Protection (OCP) In this condition the VIN terminal pin 4 decreases until
the shutdown voltage of 10V is reached. At this point
Overcurrent Protection is performed pulse-by-pulse pin 4 begins to rise again but when it reaches the start
by directly detecting the drain current of the internal up level of 16V, the latch circuit continues to stop the
power MOSFET. Since the detection voltage is drive.
monitored by an internal comparator of IC801, When the latch is on, VIN voltage at pin 4 increases
constant temperature stabilisation is also achieved. and decreases within the range 10V to 16V, as shown
The Drain-Source current through the power in the above diagram, and is prevented from rising
switching MOSFET is passed via the resistor R809, normally.
which develops a voltage across it. The input voltage
Cancellation of the latch circuit operation is achieved
to IC801 pin 1 (OCP/FB) is passed to an internal
by restarting the AC input to the circuit after switching
comparator. When this input voltage exceeds a
off the TV.
pre-determined value, the drive output is pulled LOW,
resulting in the power MOSFET switching OFF.
3.8.4. Thermal Shutdown
3.8.3. Latch This circuit triggers the latch when the body
The latch circuit is used to pull the output of the temperature of the IC exceeds 140EC. The
oscillator LOW (switching MOSFET OFF) when the temperature is sensed by the control IC, but also
over-voltage protection or thermal shutdown circuits works against overheating of the MOSFET, as both
are activated. are mounted on the same lead frame.
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3.9. Secondary Supplies output power is also reduced. This is compensated
for by the increased current flow via R853 / R854. This
On the secondary side, the transformer T802
in turn ensures that the output power of the ICs is not
supplies the following voltages:
affected.
: +12V to supply the horizontal driver stage.
: +20V to supply the East/West correction IC
IC701.
3.10. Voltage Supplies
: +27V to supply the audio output IC IC251.
3.10.1. +12V Supply
3.9.1. +12V Supply
The +12V supply is output from transformer T552 pin
The signal from pin 16 of T802 is rectified by diode 4 and is rectified by diode D553. This rectified voltage
D851 and smoothed by capacitor C856. The 12V is smoothed by capacitor C566 before being fed to the
supply voltage is then applied to the horizontal driver vertical output IC IC451 pin 6. The +12V supply also
transformer T553 via diode D501 and resistor R503. feeds the horizontal driver transformer T553 via diode
During start-up, the 12V supply feeds the horizontal D510 and resistor R503.
stage as mentioned. However, when the whole power
supply is up and running normally, the supply voltage 3.10.2. -12V Supply
from the secondary of T802 is no longer required. The
horizontal stage now takes its 12V supply from the The -12V supply is output from transformer T552 pin
FBT T552. This is required to reduce the load on the 5 and is rectified by diode D559. This negative voltage
secondary and provide drive current to the horizontal is smoothed by capacitor C564 before being fed to the
driver transformer T553. ground terminal pin 1 of the vertical output IC IC451.
3.9.2. +20V Supply 3.10.3. +10V Supply
The signal from pin 14 of T802 is rectified by diode A supply of approximately 10V is output from
D853 and applied to the series regulator IC702 to transformer T552 pin 6, and fed to diode D554. This
supply +20V to the East/West circuit (model rectified voltage signal is then smoothed by capacitor
dependant). C554 before being fed to the series regulator IC852
and the standby voltage regulator IC1202.
3.9.3. +27V Supply
3.10.4. +8V Supply
The signal from pin 14 of T802 is rectified by diode
D853 and applied to the emitter terminals of The 8V supply is derived from the 10V supply line
transistors Q851 and via resistor R855 to Q852. This which is fed to the series regulator IC852 pin 1. The
voltage to Q852 is fed via the emitter/collector output of IC852 pin 3, smoothed by capacitor C857,
junction. At the same time, the signal from pin 13 of is used to supply 8V to the TV control processor IC
T802 is rectified by diode D852 to provide a voltage IC601, RGB output stage (Y-Board) via connectors
of +27V, which is fed to the audio output IC IC251. E8 and Y2 pin 6, sound processor IC2001 and
SECAM IF audio switching IC IC201 (French models
This supply voltage of +27V however is too large for only). IC852 also supplies the 5V series regulator IC
the above mentioned ICs when under load and so the IC851.
supply voltage has to be reduced. As the load on the
above ICs increases, the voltage drop across R856
increases causing the base of Q851 to become more 3.10.5. +5V Supply
negative with respect to its emitter. With Q851 The 5V supply is derived from the 8V supply line
conducting the base bias of Q852 becomes more which is fed to IC851 pin 1. The output at pin 3,
positive with respect to its emitter, thus causing the smoothed by capacitor C851, is used to supply 5V to
supply voltage to the ICs to be reduced. the tuner, reset IC IC1105 and the sound processor
However by reducing the supply voltage to IC251, the IC2001 (model dependant).
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4. TV Signal, Control and Teletext Processing
The TDA9350/60/80 series IC601 used on Z8 used to perform control processing. The TV signal
chassis, is a one chip solution in TV processing. The and teletext processing stages will be looked at later.
Philips Ultimate One Chip (UOC) IC combines the First, the control processing stage of the UOC IC will
functions of a TV signal processor and teletext be examined.
decoder as well as an embedded microcontroller
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4.1. Control Processing Stage
The elements that the UOC IC required to perform the allows composite video and RGB signal input. Slow
control functions are: switching being provided via pin 8 for composite video
input.
: 80C51 microcontroller
: Pin 36 - EHT / Short Circuit Protection
: 12MHz internal clock
This input to the UOC IC which is normally biased by
: 32 - 128K x 8 bit late programmed ROM
R2202 and R621, provides protection by switching
: 3 - 12K x 8 bit Auxiliary RAM the TV into standby mode.
: Interrupt controller for individual enable/disable Short circuit protection is provided via transistor
Q603. The supply lines which are monitored are:
: Two 16 bit Timer/Counter registers
: +200V supply monitored by D603.
: WatchDog timer
A voltage drop in the +200V supply causes the
: Serial Interface voltage across resistor R631 to decrease. This in
turn causes diode D603 to conduct. The base of
: IDLE and Power Down (PD) mode
Q603 is held high by resistor R622. The voltage
: 14 bits Pulse Width Modulation for Voltage drop applied to the base of transistor Q603,
Synthesis Tuning causes Q603 to switch On. The protection input
at pin 36 of IC601 is now pulled High, switching
: 8 bit A/D Converter
the TV into standby.
: Programmable as general I/O, ADC input or
: +5V supply monitored by D601.
PWM (6-bit) output
A drop in the +5V supply is applied to the base
of transistor Q603, causing the transistor to
4.1.1. Input Control switch On. The protection input at pin 36 of IC601
: Pin 6 - Keyscan is pulled High, switching the TV into standby.
The local commands are fed to the UOC IC IC601 as In addition to the supplies mentioned above,
serial data. This data is input via pin 6. This pin is held protection is provided for the +8V supply, which is
at 3.3V due to the pull-up resistor R1140, which is carried out internally within the UOC IC via pins 14
connected to the 3.3V standby supply. This means and 39. When the voltage drops below the
that the High level is also maintained during standby pre-determined reference, the TV is switched into
condition. Operating commands fed from the local standby mode.
keys results in varying voltages being applied to pin Protection is also provided for the Automatic Beam
6, which in turn initiates the various controls. current Limiting (ABL) circuit via D403, discussed in
When operating commands are fed via the remote section 9.1.3.
control to pin 64 of IC601, pin 6 of IC601 also outputs
: Pin 49 - Automatic Beam Current Limiting
a pulse, which feeds transistors Q1102 and Q1107 to
provide a flashing standby LED D1104. Beam Current Limiting is performed internally within
Operating commands issued from the local and the UOC IC IC601, and is used to monitor the voltage
remote control are treated with equal status. at the BCL terminal pin 49. The brightness and
contrast varies in response to the voltage at pin 49 of
: Pin 8 - Slow Switching
IC601.
The circuit is designed so that it is possible to switch The control paths to the BCL input pin 49 is discussed
over to AV operation from all programme locations to in the CATS Eye control section 4.1.2. and Colour
the AV interface. The AV 21 pin scart socket JK3102 Output section 9.1.3.
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: Pins 58 / 59 - XTALIN / XTALOUT causes Q1107 to conduct, switching the LED D1104
On.
The internal oscillator of the UOC IC is synchronised
When an operating command is used either from the
with an external 12MHz quartz crystal X601 which is
local keys or remote control, the keyscan output pin
connected to pins 58 and 59.
6 of IC601 is pulled Low, causing transistor Q1102 to
The clock frequencies for the I2C bus system are also
switch Off. This results in the base of transistor Q1109
obtained from this frequency by internal dividing.
to go High due to pull up resistor R1146, to switch
The same 12MHz clock signal is also divided down
Q1109 On. Q1110 also conducts pulling the base of
and used to synchronise the video processing stage.
Q1107 Low, thus switching it Off. This results in the
: Pin 60 - Reset standby LED D1104 switching Off.
During power On/Off operation, or during a fall in : Pin 4 - L/L'
voltage to the UOC IC, incorrect operation may occur.
To prevent this incorrect operation, the UOC IC has Pin 4 of the UOC IC IC601 is used to select between
a reset signal input via pin 60. the two types of SECAM standards L/L'. This control
The reset signal is provided by reset IC IC1102 pin 1, signal is used on SECAM L models only.
which keeps the UOC IC in a stable condition until the : Pin 5 - CATS Eye
voltage level has risen and become stabilised. This
reset IC IC1102 which is fed a 3.3V standby supply, Pin 5 of the UOC IC is used to control a feature known
is input via pin 2. as CATS (Contrast Automatic Tracking System).
This is used to adjust the contrast level depending on
: Pin 64 - Remote IN the external light surrounding the TV. The level of the
The commands required for control of the TV receiver adjustment made is dependant upon the mode
are applied from the remote control. selected via the OSD (Medium / Maximum).
The command from the remote control transmitter is The light sensed by the LDR (Light Dependant
applied via IC1104, RPM-637BRS remote control Resistor) R1283 is used to control the conduction of
receiver to pin 64 of the UOC IC. This command data transistor Q1101 which in turn, controls the voltage
is received in serial format. level at pin 49 of IC601 and thus, the contrast level.
: Pin 7 - Neg / Pos
4.1.2. Output Control
This output control is used to select between
: Pin 1 - Standby PAL/NTSC (Negative modulation) and SECAM
This output port of the UOC IC is used to control the (Positive modulation) standards selection.
switching of the TV in and out of standby. The signal Pin 7 is also used as an input on UK models only, to
path from this output at pin 1 follows two paths. achieve the highest possible signal from the tuner via
The first path is fed via the controlling transistor Q001.
Q1204. A High level is applied from pin 1 to the base : Pin 11 - Mute
of transistor Q1204, causing Q1204 to switch On.
This in turn causes Q1201 to switch Off, preventing The mute control which is output from the UOC IC pin
current flow via the winding of the standby relay 11 is fed to the audio output IC IC251 pin 3 via Q255.
RL801. This results in the mains AC supply being Pin 11 of IC601 which is pulled Low for normal
removed from the power supply circuit. operation, is biased by resistor R1141 to the 5V
Likewise when a low level is fed to the base of Q1204, standby supply.
the transistor is biased Off, thus allowing transistor
During channel change, tuning and muting
Q1201 to conduct by a High level which is applied via
operations, the Low level output from pin 11 is
R1205. When Q1201 conducts, current via the
disabled causing the base of Q255 to go High,
standby relay causes the relay contact to close and
switching it On. This results in pin 3 of IC251 being
feed the mains AC voltage to the power circuit.
pulled Low, resulting in the audio output being muted.
The second path is fed via resistor R1141 to the Muting is also provided for audio POP during On/Off
collector of transistor Q1109. During standby, the operation via transistor Q253, the operation of which
High level applied from pin 1 to collector Q1109 is discussed in section 11.2.1.
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4.1.3. Q-Link These above features will only work with a Panasonic
TV / video combination which are both Q-Link
: Pin 62 - Q-Link_In / Pin 63 - Q-Link_Out
(Project 50+) compliant.
Q-Link input and output is a model dependant The features below will work with different brands of
function used to control the transfer of information TV and video combinations, again as long as both TV
and user functions to and from the TV / VCR via AV and video are Project 50 compliant.
21 pin socket JK3102. : Tuner preset data down load (TV->VCR)
The AV link control line fed from pin 10 of the 21 pin
AV socket is fed to the Q-Link circuit made up of : What You See Is What You Record (Direct TV)
Q1103, Q1106, Q1105 and Q1104. In addition to these features the TV/Video also
Where data is fed from the TV to the VCR, the Q-Link include in their protocol Automatic signal matching
output terminal pin 63 of the UOC IC IC601 is used. (signal quality). Here the TV/video at first time of
This results in the data being fed from pin 63 of the connecting, exchange information regarding features
UOC IC IC601 via Q1106. and operational capabilities, such as signal standards
Where data is input from the VCR to the TV, then the and the ability to process and display 16:9 format, for
Q-Link In terminal pin 62 of the UOC IC IC601 is used. example.
This results in data being fed via Q1103, Q1105 and
Q1104 to the UOC IC IC601 pin 62.
4.1.4. I2C Bus
The type of data and function control information fed : Pins 2 / 3 - SCL / SDA
via the Q-Link is as follows:
The I2C bus is a two-wire Bus system consisting of a
: TV Auto Power ON: TV automatically turns ON data line and a clock line. This BUS system allows
when the VCR starts play-back. serial and bidirectional communications exchange
between several devices which include an I2C bus
: VCR Auto Standby: VCR will automatically interface. The number of connections are therefore
switch to standby when the TV is turned OFF, reduced, which results in a simplified circuit design
unless the VCR is in recording mode. and increased reliability (less soldered
: TV On screen Display of VCR status. joints/connections and contacts).
Within the the UOC IC, the microcontroller stage and
: Download of Country selection. the signal processing stage utilise this Bus.
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4.2. Colour TV Signal Processing : Black stretching for non-standard luminance
signals
The TDA9350/60/80 series of the Ultimate One Chip
(UOC) IC IC601 incorporates all the functions : Integrated chroma bandpass filter with
necessary for processing of audio and video signals. switchable centre frequency
The following sections will include the video input and : PAL/NTSC or multistandard colour decoder with
output control, IF signal path, colour decoder and automatic search system
RGB processing stages. Horizontal and Vertical
synchronisation are also included. The elements : internal baseband delay line
required by the UOC IC to perform these functions
: RGB control circuit with 'Continuous Cathode
are:
Calibration' and colour temperature option
: Multistandard vision IF circuit with constant PLL : Linear RGB or YUV input with fast blanking for
demodulator external RGB/YUV sources
: Mono intercarrier sound FM demodulator or : Horizontal synchronisation with two control loops
QSS IF amplifier and alignment-free horizontal oscillator
: Internal IF AGC timing : Vertical count-down circuit
: CVBS (internal/external) or Y/C signal source : Vertical driver optimized for DC coupled vertical
selection output stages
: Horizontal and vertical geometry processing
: Integrated chrominance trap circuit
: Horizontal and vertical zoom function for 16:9
: Integrated luminance delay line with adjustable applications
delay time
: Horizontal parallelogram and bow correction for
: Asymmetrical peaking in the luminance channel large screen picture tubes
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4.3. IF Signal Processing from the tuner to the relevant video and audio signals
that are required.
General The IF signal is fed from the tuner TNR001 via two
The IF signal processing for the Z8 chassis is carried trap circuits, made up of X101, L105 and L106. For
out by IC601. There are two main types of IF circuit SECAM processing, the IF signal splits into two
configurations used depending on the UOC IC device paths. These are discussed in the following sections.
used, these differences will be covered in the
following sections. 4.4.1. Video (VIF) Processing Signal Path
For VIF processing of mono TVs, the IF signal is fed
4.3.1. Video (VIF) Processing Signal Path from the tuner and via the intercarrier SAW filter
The RF signal received by the tuner TNR001 is output X102. This results in the VIF signal being input via
via terminals IF1 and IF2. This IF signal is necessary pins 23 and 24 of the UOC IC IC601.
for processing of video (VIF) and sound (SIF) signals. For stereo models, the IF signal is fed via the SAW
Here the signal path varies, depending on the version filter X102 where the VIF signal is extracted before
of UOC IC used. being fed to IC601 pins 23 and 24.
For stereo models, the IF signal is passed through the
SAW filter X103, where separation of the VIF and SIF 4.4.2. Sound (SIF) Processing Signal Path
signals occur. Here, the VIF signals are fed to IC601 For mono models, the IF signal is fed from the tuner
pins 23 and 24 where video processing takes place. and via the amplifier transistor Q204 and L/L'
The internal circuit provides amplification, switching circuit, made up of transistors Q202, Q203
demodulation and filtering. The signal level is and filter X201. The L/L' operation is controlled by the
monitored by the internal AGC detector and the UOC IC IC601 pin 4 where the signal path is
information is fed back to the tuner via pin 27 of IC601. determined by the switching of the control transistor
For mono models, the IF signal path sees the IF signal Q202.
being fed to the intercarrier SAW filter X102. From During L mode operation, pin 4 of IC601 is pulled low
here the signal feeds the UOC IC IC601 via pins 23 causing transistor Q202 to be switched Off. With the
and 24 where video processing takes place internally. voltage at the collector of Q202 being High, the IF
signal will flow via transistor Q204, diode D202 and
pin 2 of filter X201. At the same time, transistor Q203
4.3.2. Sound (SIF) Processing Signal Path
switches on causing the L' input pin 1 of X201 to be
As already mentioned, the IF signal fed from the tuner pulled Low, muting its operation.
is necessary for the processing of sound (SIF) During L' mode operation, pin 4 of IC601 is held high
signals. Once again, the signal path varies, by resistor R209 causing transistor Q202 to switch
depending on the version of UOC IC used. on. The voltage at the collector of Q202 is Low,
causing the IF signal to flow via transistor Q204,
For stereo models, the SIF signal fed from the SAW
diode D201 and pin 1 of filter X201. At the same time,
filter X103 is applied to IC601 pins 28 and 29, where
the L input pin 2 of X201 is pulled Low via transistor
signal processing is provided internally within the IC.
Q203, muting its operation.
Here the signal is split into two paths.
The SIF signal from X201 is fed via the IF inputs pins
The first path feeds the signal through an internal 1 and 16 of the AM demodulator/audio switch IC201.
Quasi Stereo Sound (QSS) mixer and bandpass filter, The audio output at pin 8 is fed to the buffer transistor
to produce a QSS IF output at pin 35 via the audio Q208. Transistor Q209 is used to provide muting of
switching circuit. the audio signal when no SECAM signal is present at
the tuner input. Pin 7 of IC601 provides the trigger
For mono models, the SIF signal path is fed to IC601 voltage to Q209, the level being determined by the
pins 23 and 24 via the intercarrier SAW filter X102. As presence of either positive (SECAM) or negative
already mentioned, separation of the VIF and SIF (PAL/NTSC) modulation. From here the signal
signals occur internally within the UOC IC. follows two paths.
The first path feeds the audio signal to the UOC IC
IC601 pin 28 for further processing.
The second path sees the audio signal being output
4.4. SECAM IF Signal Processing via transistors Q3101 and Q3102 to the AV 21 pin
scart pins 1 and 3.
For stereo models, the IF signal is fed from the tuner
General via the amplifier transistor Q204 and L/L' switching
Those models which are capable of processing circuit as mentioned above. The SIF signal from X201
SECAM L signals have an additional IF signal path is fed via pins 28 and 29 of the UOC IC IC601.
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4.5. Video Signal Processing resultant VIF signal being output via pin 38.
The SIF signal however, is input via pins 28 and 29,
General the processing of which is discussed in section 4.3.2.
The UOC IC IC601 carries out all the necessary On mono models, the VIF / SIF signals are again fed
control operations required for video and audio from the tuner via the IF stage. The IF signals are both
processing. input via pins 23 and 24 to the first processing stage,
which again provides amplification, demodulation
On stereo models, the VIF signal is fed from the tuner and filtering. Here the VIF and SIF signals follow
via the IF stage (discussed in section 4.3.1.) pins 23 different processing paths, which results in the VIF
and 24. Here the VIF signal is fed to the first signal again being output via pin 38, and the SIF
processing stage of IC601, which provides signal being fed to the internal audio processing stage
amplification, demodulation and filtering, with the of IC601 discussed in section 4.7.
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4.6. Video Processing Here the chroma signals are demodulated with the
resultant U/V signals being fed to the following
The VIF signal fed from the first stage of IC601 is
baseband delay line, which ensures the chrominance
output via pin 38, as mentioned in the previous
and luminance signals are at the same timing.
section.
The U/V signals are then fed to the RGB processing
At the output of pin 38, the VIF signal is fed back to
stage.
transistor Q601 where the VIF signal is buffered and
fed via a sound trap. This sound trap which is model Timing and synchronisation of the colour decoder
dependant, may consist of L601, X602, X603, L603 processing stage is achieved by using a 12MHz clock
and X604. The VIF signal is then fed to buffer signal fed from an internal reference oscillator of the
transistor Q602 and is output at the emitter. Here the microcontroller stage. During SECAM processing,
video signal is split into two paths. this timing and synchronisation of the colour decoder
: The first path sees the video signal being fed via stage is achieved using the 12MHz clock and is set by
the buffer transistor Q3104, to pin 19 of the AV C604, located at pin 13 of IC601.
21 pin scart terminal.
: The second path from the emitter of Q602 feeds 4.6.3. RGB Processing Stage
the video signal back to IC601, where the signal The luminance and chrominance signals fed from the
is input via pin 40. previously discussed processing stage are fed to a
switching circuit within the RGB processing stage.
The video signal which is input via pin 40 is fed to the
Here at this switching circuit, the RGB and fast
internal stages consisting of a video switch, video
blanking signals input via the AV 21 pin scart terminal
ident and filters. The video switch of this stage is used
(JK3102) pins 15, 11 and 7 respectively, are fed to
to select between following signals:
IC601 pins 46, 47 and 48 with the blanking signal
: RF video input via pin 40 as already discussed. being input via pin 45.
: Video input via pin 42, this video signal being The signals fed to the switching circuit are firstly fed
input via either the RCA video (located at the via and RGB to YUV converter. From here the newly
front of the TV) or pin 20 of the AV 21 pin scart converted YUV signals are then fed to the YUV
switching circuit.
terminal.
This YUV switching circuit which is controlled by the
The selected video signal is then fed to the video ident fast blanking pulse input via pin 45, is used to select
stage, which is used to detect the presence of a video between the internally processed luminance and
signal input via either pin 40 or 42. Where a video chrominance signals and newly converted YUV
signal is present at the input of IC601, internal signals.
synchronisation using the video signal occurs. The selected signals being fed via a saturation control
However, where the absence of a video signal is stage are then converted to RGB. The RGB signal is
detected, then synchronisation is internally then fed to the RGB stage of IC601.
generated.
The selected video signal is also fed via the video 4.6.4. RGB Output Stage
filters which produce luminance and chrominance
In this final processing stage of IC601 the RGB
signals that follow separate processing paths.
signals from the RGB processing stage and the RGB
from the text / OSD generator (discussed in section
4.9.1.) are fed to a switching circuit. The selected
4.6.1. Luminance Processing RGB signal is then fed via the contrast and brightness
control stages, which are also controlled by the Beam
The luminance signal is now fed via a delay line,
Current Limit (BCL) information input via pin 49 of
which compensates for the processing time
IC601, as well as information fed from the CATS Eye
difference between the luma and chroma signals. The
circuit.
luma signal is fed via a peaking circuit and a black
The RGB signal is then fed via the RGB output
stretch correction stage, which provide black level
amplifiers, which are controlled by the leakage and
correction. The luma signal is then fed to the RGB
cutoff currents (discussed in section 8.1.1.) fed back
processing stage.
from the colour output stage to IC601 via pin 49.
The RGB signal is then finally output from IC601 via
4.6.2. PAL Chrominance Processing pins 51 (R), 52 (G) and 53 (B). The RGB signal is then
To process chroma signals, the output from the video fed to connector E8 where this signal is fed to the
switching circuit is fed to the colour decoder stage. Y-Board and the colour output stage.
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4.7. Audio Signal Processing processing stage, provides amplification and filtering
using an internal bandpass filter.
As already mentioned in section 4.3.2. the SIF signal
The SIF signal is then fed via the following
fed from the tuner follows a number of different paths
demodulator stage to the audio switch and Automatic
dependant upon the model and UOC IC IC601
Volume Level (AVL) control stage. Also input directly
(TDA9350/60/80 series).
to this stage via pin 35 of IC601 is the audio signal
input via either the 21 pin scart terminal or the RCA
4.7.1. Stereo Models terminal.
The SIF signal input via pins 28 and 29 of IC601 are Here these signals are fed to a selection switch where
processed internally, with the signal being fed via a the selected audio signal is then fed to the AVL control
Quasi Stereo Sound (QSS) mixer and bandpass filter stage, this feature being model dependant.
which is used to produce a QSS IF output at pin 35 The AVL control stage is used to automatically
of IC601. stabilise the audio signal output to a set level,
This QSS IF signal is then fed via transistors Q2004 reducing the effects of varying audio levels which
/ Q2003 to the MSP3415D pin 47 of IC2001 occur between different programmes.
(described in section 10.). The audio signal is then output via pin 44 of IC601,
where the signal is then fed to the audio output IC
IC251.
4.7.2. Mono models
The audio signal output via pin 28 of IC601 to
On mono models the UOC IC IC601 internal
transistors Q3101 and Q3102 where the signal is
processing differs from that used by the stereo
amplified and buffered before being fed to pins 1 and
versions of the UOC IC.
3 of the 21 pin scart terminal.
The SIF signal fed from the tuner is input via pins 23
and 24. Here the SIF signal which is fed via the first
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4.8. SECAM Audio Signal Processing mono version of the UOC IC IC601 does not contain
an AM demodulator stage.
4.8.1. Stereo Models This AM signal which is output from X201 is fed to
IC201 pins 1 and 16. The resultant signal is output at
On SECAM stereo models, the SIF signal is input via
pin 8 and fed via emitter follower transistor Q208. This
pins 28 and 29 where the processing mentioned in
AM SIF signal is then split into two paths as discussed
section 4.4.2. is performed. This results in a QSS IF
in section 4.4.2, with one path feeding the AM audio
signal being output via pin 35. This signal being fed
signal to pin 28 of IC601.
via transistors Q2004 and Q2003 to the MSP3415D
Here the audio signal undergoes the processing
pin 47 of IC2001 (discussed in section 10.).
discussed in section 4.7.2. which results in the audio
Where an AM audio signal is required for further signal being fed via the Automatic Volume Level
sound processing, the SIF signal is passed through (AVL) control stage.
an AM demodulator and output via pin 44. This signal The audio signal is then output via pin 44 of IC601,
being fed to the MSP3415D pin 44 of IC2001 where the audio signal is fed to the audio output IC
(discussed in section 10.). IC251. The audio signal which is output from the 21
pin scart terminal is fed from IC201 via transistors
4.8.2. Mono Models Q3101 and Q3102.
On SECAM mono models, an FM modulated SIF
It should be noted that pin 28 of IC601 has two
signal fed from the tuner is also input via pins 23 and
functions depending on the signal being processed.
24 (mentioned in section 4.4.).
Where SECAM signals are being processed, pin 28
However, where an AM modulated SIF signal is is an input for the AM SIF signal fed from IC201.
received, this signal is fed to an additional IC in the For PAL / NTSC operation, pin 28 is an output which
form of IC201 (TDA9830), discussed in section 12.1. allows the audio signal to be fed to the 21 pin scart
This IC is required to demodulate the AM signal as the terminal.
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4.9. Teletext Processing Stage : Comprehensive teletext language coverage
: Full Field and Vertical Blanking Interval (VBI)
General data capture of WST data
In addition to the TV signal and control processing
capabilities of the UOC IC IC601 already briefly 4.9.1. Teletext Operation
mentioned earlier, the device also performs teletext
To enable teletext processing, the CVBS signal and
processing. The features included within the IC to
sync pulse is applied to the teletext acquisition stage.
perform teletext processing are shown below.
Here the signal is converted into a digital form and the
: Text memory for 1 or 10 pages synchronisation information is used to produce a
display.
: Data Capture for US Closed Caption
The acquisition stage extracts the transmitted text
: Data Capture for 525/625 line World System
data and stores it into the page memory, where it is
Teletext (WST), Video Programme Signal (VPS)
held until this data is requested. The microcontroller
and Wide Screen Signalling (WSS) bit decoding
detects the requisition of the teletext data and when
: Automatic selection between transmission selected, the information is fed to the display/OSD
systems generator. The pixel information from the page
memory is translated into RGB values. The
: Real time capture and decoding for WST in
generation of the pixel clock is created internally by
hardware, to enable optimized UOC IC
the display timing stage which is fed a horizontal and
throughput
vertical sync signal via the internal drive circuits.
: Automatic detection of FASTEXT transmission
The RGB text data and fast blanking information is
: Signal quality detector for video and WST/VPS translated via the internal RGB processing stage. The
data types output path is described in section 4.6.4.
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4.10. Synchronisation and Deflection : S-correction
Processing : Vertical shift
The UOC IC IC IC601 contains separator circuits for For those models which have East-West correction
the horizontal and vertical sync pulses. These signals included, the additional adjustments are given below.
are used to produce the horizontal, vertical and E/W
drive pulses. Synchronisation is processed internally : EW width
within IC601. This processing circuit allows the : EW parabola width
following geometry parameters to be adjusted, which
are carried out by software control. : EW upper and lower parabola correction
: Horizontal shift : Vertical zoom
To carry out synchronisation and deflection
: Vertical amplitude
processing, the luma signal from the video switch
: Vertical slope circuit is applied to the internal sync separator.
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4.10.1. Horizontal Drive Processing incoming flyback pulse which is used to provide
horizontal blanking of the RGB outputs
The horizontal signal fed from the sync separator is
passed via an internal PLL which is controlled by a
25MHz Voltage Controlled Oscillator (VCO). 4.10.3. Geometry Processing
The horizontal drive pulse is then output from pin 33 The vertical pulse fed to the vertical sawtooth or ramp
of IC601, synchronised by the horizontal flyback generator is then processed, thus producing a
pulse input via pin 34. sawtooth whose amplitude is determined by the
The horizontal output frequency decreases from external RC components at pins 25 and 26 of IC601,
35KHz to 15.625KHz during switch On/Off times, made up of R603 and C614. The output path of the
thereby reducing the load on the horizontal output vertical sawtooth generator is split into two paths.
transistor Q501 during these periods. The first path sees the signal being input to the
vertical geometry processor. This provides a
4.10.2. Vertical Processing differential drive signal which is output from pins 21
and 22, and fed to the vertical output IC IC451 pins 4
The vertical pulse produced by means of a vertical (V+) and 5 (V-).
divider circuit is fed a vertical sync signal and is output
The second path feeds the East-West (EW) geometry
from the separator stage. This pulse is fed to a vertical
processor. This function is available for large screen
sawtooth generator, which is used to produce the
TVs of 25" and above, and is used to provide
vertical and EW drive signals. The vertical pulse is
additional vertical correction. The EW drive to the
also input to the sandcastle generator which outputs
correction stage is output from pin 20 of IC601.
a two level sandcastle pulse via pin 34. The clock
signal to the vertical divider is achieved by means of An overvoltage protection input is provided at pin 36,
a burstkey pulse fed from the horizontal oscillator. which is fed via the ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo