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An Overview of the Mesa Processor Architecture
Richard K. Johnsson
John D. Wick
Xerox Office Products Division
3333 Coyote Hill Road
Palo Alto. California 94304
Introduction example of how the Mesa instruction set enables
significant reductions in code size over more traditional
This paper provides an overview of the architecture of the
architectures. We will also discuss in considerable detail
Mesa processor. an architecture which was designed to
the control transfer mechanism used to implement
support the Mesa programming system [4]. Mesa is a high
procedure calls and context switches among concurrent
level systems programming language and associated tools
processes. A brief description of the process facilities is
designed to support the development of large information
processing applications (on the order of one million source also included.
lines). Since the start of development in 1971. the
processor architecture. the programming language, and the General Oveniew
operating system have been designed as a unit, so that All Mesa processors have the following characteristics
proper tradeoffs among these components could be made. which distinguish them from other computers:
The three main goals of the architecture were:
High Level Language
- To enable the efficient implementation of a
modular, high level programming language such as The Mesa architecture is designed to efficiently execute
high level languages in the style of Algol, Mesa, and
Mesa. The emphasis here is not on simplicity of the
compiler, but on efficiency of the generated object Pascal. Constructs in the programming languages such as
code and on a good match between the semantics of modules, procedures and processes all have concrete
the language and the capabilities of the processor. representations in the processor and main memory, and
the instruction set includes opcodes that efficiently
- To provide a very compact representation of implement those language constructs (e.g. procedure call
programs and data so that large, complex systems and return) using these structures. The processor does not
can run efficiently in machines with relatively small "directly execute" any particular high level programming
amounts of primary memory. language.
- To separate the architecture from any particular Compacl Program Representation
implementation of the processor, and thus
accommod~te new implementations whenever it is
The Mesa instruction set is designed primarily for a
technically or economically advantageous, without compact, dense representation of programs. Instructions
materially affecting either system or application are variable length with the most frequently used
software. operations and operands encoded in a single byte opcode;
less frequently used combinations are encoded in two
We will present a general introduction to the processor bytes, and so on. The instructions themselves are chosen
and its memory and control structure; we then consider an based on their frequency of use. This design leads to an
asymmetrical instruction set For example, there are
Permission to copy without fee all or part of this material is granted
provided that the copies are not made or distributed for direct twenty-four different instructions that can be used to load
commercial advantage, the ACM copyright notice and the title of the local variables from memory, but only twenty-one that
publication and its date appear, and notice is given that copying is by
store into such variables; this occurs because typical
permission or the Association for Computing Machinery. To copy
otherwise, or to republish, requires a ree and I or specifIC permission. programs perform many more loads than stores. The
average instruction length (static) is 1.45 bytes.
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