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Papers from the SunDragon Project
Papers from the SunDragon Project


A CMOS Low Voltage Swing Transmission Line Transceiver,                                    by Bill
Gunning, Leo Yuan, Trung Nguyen, and Tony Wong.
XDBus: A High-Performance, Consistent, Packet-Switched VLSI Bus,             by
Pradeep Sindhu, Jean-Marc Frailong, Jean Gastinel, Michel Cekleov, Leo Yuan, Bill
Gunning, and Don Curry.
The Next-Generation SPARC Multiprocessing System Architecture, by
Jean-Marc Frailong, Michel Cekleov, Pradeep Sindhu, Jean Gastinel, Mike Splain,
Jeff Price, and Ashok Singhal.
SPARCcenter 2000: Multiprocessing for the 90's! by Michel Cekleov, David
Yen, Pradeep Sindhu, Jean-Marc Frailong, jean Castinel, Mike Splain, jeff Price,
Gary Beck, Bjorn Liencres, Fred Cerauskis, Chip Coffin, Dave Bassett, David
Broniarczyk, Steve Fosth, Tim Nguyen, Raymond Ng, Jeff Hoel, Don Curry, Leo
Yuan, Roland Lee, Alex Kwok, Ashok Singhal, Chris Cheng, Greg Dykema, Steve
York, Bill Gunning, Bill jackson, Atsushi Kasuya, Dean Angelico, Marc Levitt, Medhi
Mothashemi, David Lemenski, Lissy Bland, and Tung Pham.
The Years of the Dragon               reprinted from "Benchmark" magazine, Spring 1993.


CSL-93-17             December 1993 [93-00139]

~   Copyright 1993 Xerox Corporation. All rights reserved.


CR Categories and Subject Descriptors: B.3.2 [Design Styles]: cache memory,
shared memory; C.1.2 [Multiple Data Stream Architectures]: MIMP processors, C.O
[General]: system architectures; B.4.3 [Interconnection]: VLSI bus interconnect,
backplanes; B.7.1 [Types and Design Styles]: Advanced technologies, input/output
circuits




                                                             Xerox Corporation
XEROX                                                        Palo Alto Research Center
                                                             3333 Coyote Hill Road
                                                             Palo Alto, California 94304
Introduction



From 1988 to 1992 a remarkable cooperation took place between the Computer
Science Lab at Xerox PARC and Sun Microsystems.             The CSl "Dragon"
multiprocessor research project moved in with a development team at Sun to
create a series of Sun products based on the Dragon team's inventions in bus and
memory architecture.    The business details are beyond the scope of this tech
report -- but now that products are shipping, accountants on both sides seem to
be very happy.

Here are five internal reports on aspects of the SunDragon project, as it came to
be known. All are also scheduled to be published elsewhere, as indicated with
each paper.    "A CMOS low Voltage Swing... " describes the basic logic design,
known as GTl (Gunning-Transistor-logic) for the SunDragon bus.          "XDBus: ... "
describes the logic for the bus itself, including its support for cache consistency
and its packet-switched protocol.    "The Next Generation ... " describes the fuller
system architecture of the Sparcenter 2000-'s use of the XDBus as the heart of a
commercial scalable multiprocessor.    "SPARCenter 2000: ... " briefly describes the
full SPARCenter 2000 system from a user perspective.       Finally, "The Year of... "
offers some commentary and interviews from Sun and Xerox on the process of this
unusual cooperation.

In closing, let me honor and acknowledge Jean Gastinel, leader of the Dragon
project, whose vision saw the opportunity with Sun and whose technical and
managerial leadership made it a success.



          Mark Weiser
          Head, Computer Science Lab




                                                                           LUM4 UM; ,#   #.   ;
                A CMOS Low Voltage Swing Transmission Line Transceiver
                               Paper WP3.7



 Authors:
 Bill Gunning 415-336-1194 (tel) 415-964-0706 (fax)
 XeroxPARC
 3333 Coyote Hill Road
 Palo Alto, Ca 94304

 Leo Yuan 415-336-3841 (tel) 415-964-0706 (fax)
 Sun Microsystems MfV 16-10
 1501 Salado Drive
 Mountain View, Ca 94043

 Trung Nguyen 408-433-7546 (tel) 408-434-6457 (fax)
 LSI Logic
 1551 McCarthy Blvd.
 Milpitas, Ca 95035

 Tony Wong 408-433-7539 (tel) 408-434-6457 (fax)
 LSI Logic
 1551 McCarthy Blvd.
 Milpitas, Ca 95035




Abstract

CMOS I/O circuits designed for terminated transmission line inter-chip
communication are described. The nominal signal swing (800 m V) and signal

quality are comparable with ECL systems. Typical on-chip power is 15 mW

per I/O. Several ASICs with 160 I/Os have been built.




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