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XEROX
Office Products Division
Office Systems Business Unit
To: Ed Miller Date: June 18, 1981
From: Roy Ogus Org: SDD/SD&T Workstation Design
Subject: Opportunities for Dandelion Cost Reduction
Filed: [lris]232C/RS306 controller is about 30 equlvalent chips. The cost savings would be more than a $l-
a-chip since there are several LSI components in the two controllers. The Raven controller would
save approximately $30, while the RS232C controller could save about $60.
lOP Module
Removal of Floppy Disk Controller
A savings of about 28 equivalent chips (approximitely $40) can be achieved if the floppy disk
controller is removed from the lOP. There would be an additional savings of about $300 for the
removal of the drive. This change can probably only be contemplated for a workstation machine,
which has Etherbooting implemented.
There are other implications in removing the floppy disk. The diagnostics are run from the floppy
disk, and cases where the CP does not function, the machine can still be diagnosed from the lOP.
This would not be possible if there was no floppy disk, since the diagnostics would have to be
fetched from the Ethernet, requiring the CP to be functional. In addition, software distribution is
. currently achieved using floppy disks. This would have to be redesigned to allow distribution over
the Ethernet Initialization of a server machine on a newtwork with no other servers can, of course,
not do without the floppy disk
Conve.rsion to CMOS Time-of Day circuit in Maintenance Panel
The original Time-of-Day (TOO) circuit which was designed for the Dandelion was implemented in
CMOS logic, stored entirely on the Maintenance Panel module. On recommendation of the
ED/Parts group this design was abandoned in favor of a completely TTL design. This had the
effect of requiring additional space on the lOP module to house the most of the TOD circuitry. If
the original TOO circuit was re-used, then 12 chips on the lOP could be dispensed with. There still
might have to be qualification activity on some of the parts. This savings is small, and also does
not free up enough room on the lOP to allow moving any other function. This change is
documented here for the record.
Opportunities for Dandelion Cost Reduction' 6
Conclusions
This section summarizes the potential savings described above. Note that some of the techniques
have little or no effect on the system operation, while others have a large impact This impact
should first be evaluated before considering using the cost-reduction technique.
64K Dynamic RAMs. This technique is clearly one that should be implemented. The economics
are such that the 64K-based system is on the verge of being (or is already) cost-effective.
Considerations still to be resolved are the availability of 64K parts, and the qualification of
suitable vendors for supply.
Removal of Error Correction Logic. More data on and analysis of 64K memory failure rates in the
system is needed before this technique should be considered.
Higher density RAM Control Store. This change is attractive since it frees up 36 chip locations on
the CP card, an is a relatively simple change to implement. However, there is still some risk
in that the 2168 parts are still not available in production quantities. It is expected that this
will not be a problem in 1982.
Prom Control Slore. This change should be considered with great caution. The appropriate Prom
chips are not yet available, and thus not qualified or second-sourced. It is not clear yet
whether Prom usage will result in a cost savings (or at least initially). But most importantly,
this change has a large impact on the system operation. The ramifications of a Prom control
store on booting, diagnostics operation, and handling of system changes, should be studied
carefully before deciding to implement the change.
CMOS Control Store RAMs. It is difficult to put a value on the cost savings of this change, since
the savings will be in life-cycle costs due to increased reliability (hopefully). Other benefits
of this change are to reduce the load on the + SV power supply, thus increasing the overload
margin when the 64K-based memory is used.
Removal of Raven and/or RS232C Controller. This savings can only be realized in machines that
can dispense with these functions. Other benefits will occur if other savings together with
these result in the entire Options card being able to be dispensed with.
Removal of Floppy Disk Controller. This savings can be achieved in machines that do not need the
floppy disk. This will depend on Etherbooting being implemented, and the corresponding
software changes to initialize the rigid disk from the Ethernet There are also Field
implications, in that diagnostics, and distribution of software will have to be redesigned.
CMOS Time-of Day circuit. A relatively small savings is achieved using this technique. It might
have the added benefit of isolating the TOD from the system in a better manner than is now
done, perhaps reducing the interference problems in the TOD circuitry.
Thus, the recommended cost reductions are the use of 64K memory chips, and the 4Kx4 control
store chips. In addition, the Raven and RS232C controllers may be dispensed with in certain
configurations.
A significant savings will be achieved if the Dandelion can be reduced to a 4-board machine
(Memory Control, CP, lOP, and HSIO). Implementing the 64K-based memory system, using the
4Kx4 control store chips, and removing the RS232C and Raven controllers, still does not allow the
Options card to be removed since the Ethernet controller (almost 100 equivalent chips currently) has
to placed on the other boards, which do not obviously have the space. More work needs to be done
to determine how to remove the fifth board (if that is possible).
Opportunities for Dandelion Cost Reduction 7
Longer Term Cost Reduction Opportunities
The changes described in this section are those which are not immediately feasible. This may be
due to a substantial development effort being required, together with the implementation of new
design tools. Alternatively, the change may be dependent on usage of vendor components which
are not yet available.
a) Ethernet controller
Intel and other vendors are currently developing LSI components specially designed to implement
Ethernet controllers for LSI microprocessor systems. These compQnents are more than 18 months
from being in production.
It is not apparent to me that the Intel Ethernet controller chip (82D2-E) would allow any cost
reduction in the Dandelion Ethernet controller. It is speciafically designed to interface to an 8086-
like bus structure which is not compatible with the Dandelion I/O controller bus structure. A
reasonable amount of logic would have to be implemented to convert between the two bus
structure, and this could offset any potential savings through the use of the LSI controller. The
82D2-E interfaces to the processor through memory, and thus a two-ported memory system would
have to be aoded to the controller for communications to thl': CPo
The Intel Ethernet Serial Interface (ESI) chip, however, applears to fit in more easily with the
current controller structure. The ESI integrates the front-end controller functions such as
transceiver interfacing, and data stream encoding and decoding (phase-lock loop). Using the ESI
chip could save approxiately 14 chips and about 60 discretes in the Ethernet controller.
b) Gate Array usage
This section takes a first look at the potential for implementing parts of the Dandelion CP module
using gate-array techniques. The available Texas Instruments gate array components were used as
the basis the study.
Assuming that as much of the CP was converted to gate array implementation, then the Dandelion
CP could be implemented with the following components:
? Control-Store chips (depends on whether RAM or Prom)
7 Gate Array Chips
11 RAM Memory Chips (4-256x4, 7-16x4)
4 2901 ALU Chips
15 MSI Chips
In some cases, it may not make sense to implement the section of random logic in gate arrays, since
it still may be cheaper to implement the random logic. However, this analysis serves to illustrate
the largest savings in chips that would be possible.
The details of the gate array chips are as follows:
LRot-StkP-IB-NibByte
replaces 29 Ie's
contains 1000 gates
has 67 I/O signals
Opportunities for Dandelion Cost Reduction 8
NIAD.. 7
replaces 7+ IC's
contains 294 gates
has 64 110 signals
NI,AB.. l1
replaces 9+ IC's
contains 192 gates
has 66 1/0 signals
FDecodes
replaces 7+ Ie's
contains 160 gates
has 64 1/0 signals
Erro,. Kern-Task
replaces 9+ Ie's
contains 337 gates
has 71 110 signals
Carry-Shift-DispBr
replaces 7+ IC's
contains 156 gates
has S2 110 signals
Clock-Ma,.Misc
replaces 9+ Ie's
contains 189 gates
has 67 1/0 signals
Appendix A contains the full details of what logic in the CP is replaced by the various gate array
chips
Opportunities for Dandelion Cost. Reduction 9
Appendix A: Gate Array Component Details
Following are the details of the gate arrays referenced in the memo. The numbers in braces
indicate the number of gate array gates required for each chip which is replaced. The TI gate
arrays were used as basis of this study. The information on the gate array implementations was
provided by Don Charnley.
LRot-StkP-IB-NibByte
8257 {64}
2S809 {45}
LS283 {60}
25809 {45}
8240 {9}
8373 {8I}
8373 {8I}
8374 {65}
8260(1/2) {7}
L8374 (2/4) {33}
F934S3 {20}
F93453 {20}
2S810 {40}
25810 {40}
2S810 {40}
25810 {40}
S241 {16}
S257 {64}
S257 {64}
S257 {64}
8241(4/8) {8}
8241 (4/8) {8}
8138 [3/8] {IO}
8138[1/8] {4}
S138 [2/8] {7}
S138[5/8] {16}
800 (1/4) {I}
SOO (1/4) {I}
820 (112) {I}
820 (112) {I}
F93453 (1/4) {10}
810 (1/3) {I}
800 (1/4) {I}
SlO (1/3) {I}
800 (1/4) {I}
8138 [3/8] {IO}
8374 [4/8] {33}
LS32 (1/4) {3}
S02 (1/4) {3}
Inputs:
X.O.XIS
Y:O ..Y.IS
1S.0.. 1S.3
IX.O.. IXJ
fY.O .. fYJ
pfZ.O..pfZJ
pfS.2, pSE, AlwaysClk, WaitClk, ppCLK
Wait, AllowMDR", MesaInt
Opportunities for Dandelion Cost Reduction 10
Outputs:
IB.0..IB.7
IBEmptyErr. EKErr.O'. EKErr.l'
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