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see
USER's
MANUAL
Contains Specifications for
the following Zilog parts:
Z8030 Z8530
Z80C30 Z85C30
Z80230 Z85230
Z85233
see
USER's
MANUAL
Contains Specifications for
the f!lllowing Zilog parts:
Z8030 Z8530
Z80C30 Z85C30
Z80230 Z85230
Z85233
Q4/92
Preface
Thank you for your interest in the SCC (Serial Communica- you have previously used the Z80 SIO, you will find these
tion Controller) family of products. devices, which share much the same basic architecture, to
be very familiar.
This manual is intended as a technical resource for part
numbers Z8030, Z80C30 and Z80230 (Z-Bus) as well as The document is organized into nine chapters as follows:
Z8530, Z85C30, Z85230, and Z85233 (Universal Bus). If
1. General Description
Chapter 1 is an introductory section covering the key features and giving an
overview of block diagrams, pin-outs, pin definitions and signal functions.
2. Interfacing the SCC/ESCC
Chapter 2 provides all of the technical information to describe the bus inter
faces. Included are timing diagrams, register accesses, resets, interrupts,
Read/Write cycles, programming, OMAs and test functions.
3. SCC/ESCC Ancillary Support Circuitry
Chapter 3 covers the SCC's/ESCC's functional details in the areas of baud rate
generator, data encoding/decoding, digital phased-lock loop (NRZI, FM,
Manchester modes), transmit clock counter, clock selection and crystal
oscillator.
4. Data Communication Modes
Chapter 4 explains the transmit/receive data paths, asynchronous modes, byte-
oriented synchronous modes, and bit-oriented synchronous (SOLC/HOLC)
modes.
5. Register Descriptions
Chapter 5 illustrates and explains all of the bit and byte functions of the
Read/Write registers.
6. Z85C30 SL 1480 Enhancements
Chapter 6 explains the SOLC enhancements.
Application Notes
This section provides examples and useful tips to aid in development of
SCC/ESCC Applications.
Questions and Answers
This section contains Answers to the most comrn:)nly asked SCC/ESCC
Questions.
Support Products
This section contains descriptions of development tools used to support the
SCC/ESCC.
Table of Contents
Chapter 1
1.1 Introduction ............................................................................................................................................................. 1-1
1.2 SCC's Capabilities .................................................................................................................................................. 1-2
1.3 Block Diagram ........................................................................................................................................................ 1-4
1.4 Pin Descriptions ................................................................................................................................, ..................... 1-5
1.4.1 Pins Common to both Z85X30 and Z80X30 ................................................................................................. 1-7
1.4.2 Pin Descriptions, (Z85X30 Only) .................................................................................................................. 1-8
1.4.3 Pin Descriptions, (Z80X30 Only) ....................................................................................,............................. 1-9
Chapter 2
2.1 Introduction .............................................................................................................................................................2-1
2.2 Z80X30 Interface Timing ........................................................................................................................................2-1
2.2.1 Z80X30 Read Cycle Timing .........................................................................................................................2-2
2.2.2 Z80X30 Write Cycle Timing .......................................................................................................................... 2-3
2.2.3 Z80X30 Interrupt Acknowledge Cycle Timing ............................................................................................. 2-4
2.2.4 Z80X30 Register Access ..............................................................................................................................2-5
2.2.5 Z80C30 Register Enhancement ................................................................................................................... 2-8
2.2.6 Z80230 Register Enhancements .................................................................................................................. 2-8
2.2.7 Z80X30 Reset ...............................................................................................................................................2-9
2.3 Z85X30 Interface Timing ......................................................................................................................................2-10
2.3.1 Z85X30 Read Cycle Timing ....................................................................................................................... 2-10
2.3.2 Z85X30 Write Cycle Timing ........................................................................................................................ 2-11
2.3.3 Z85X30 Interrupt Acknowledge Cycle Timing ........................................................................................... 2-11
2.3.4 Z85X30 Register Access ............................................................................................................................2-12
2.3.5 Z85C30 Register Enhancement .................................................................................................................. 2-14
2.3.6 Z85230 Register Enhancements ................................................................................................................ 2-14
2.3.7 Z85X30 Reset .............................................................................................................................................2-14
2.4 Interface Programming .........................................................................................................................................2-15
2.4.1 I/O Programming Introduction .................................................................................................................... 2-15
2.4.2 Polling ........................................................................................................................................................2-16
2.4.3 Interrupts ....................................................................................................................................................2-16
2.4.4 Interrupt Control ......................................................................................................................................... 2-17
2.4.5 Daisy-Chain Resolution ..............................................................................................................................2-19
2.4.6 Interrupt Acknowledge ...............................................................................................................................2-21
2.4.7 The Receiver Interrupt ................................................................................................................................2-21
2.4.8 Transmit Interrupts and Transmit Buffer Empty Bit ..................................................................................... 2-25
2.4.9 External/Status Interrupts ........................................................................................................................... 2-29
2.5 Block/DMA Transfer .............................................................................................................................................. 2-31
2.5.1 Block Transfers ..........................................................................................................................................2-31
2.5.2 DMA Requests ...........................................................................................................................................2-34
2.6 Test Functions ......................................................................................................................................................2-39
2.6.1 Local Loopback .........................................................................................................................................2-39
2.6.2 Auto Echo ...................................................................................................................................................2-39
Chapter 3
3.1 Introduction .............................................................................................................................................................3-1
3.2 Baud Rate Generator ..............................................................................................................................................3-1
3.3 Data Encoding/Decoding .......................................................................................................................................3-4
3.4 DPLL Digital Phase-Locked Loop .......................................................................................................................... 3-7
3.4.1 DPLL Operation in the NRZI Mode ..............................................................................................................3-8
3.4.2 DPLL Operation in the FM Modes ................................................................................................................ 3-9
3.4.3 DPLL Operation in the Manchester Mode .................................................................................................3-11
3.4.4 Transmit Clock Counter (ESCC only) ......................................................................................................... 3-11
3.5 Clock Selection .....................................................................................................................................................3-12
3.6 Crystal Oscillator ..................................................................................................................................................3-15
Chapter 4
4.1 Introduction ............................................................................................................................................................4-1
4.1.1 Transmit Data Path Description ...................................................................................................................4-1
4.1.2 Receive Data Path Description .................................................................................................................... 4-2
4.2 Asynchronous Mode ..............................................................................................................................................4-3
4.2.1 Asynchronous Transmit ................................................................................................................................4-4
4.2.2 Asynchronous Receive ................................................................................................................................4-6
4.2.3 Asynchronous Initialization ...........................................................................................................................4-7
4.3 Byte-Oriented Synchronous Mode ......................................................................................................................... 4-8
4.3.1 Byte-Oriented Synchronous Transmit ............................................................................ :............................. 4-9
4.3.2 Byte-Oriented Synchronous Receive ......................................................................................................... 4-12
4.3.3 Transmitter/Receiver Synchronization ........................................................................................................4-18
4.4 Bit-Oriented Synchronous (SDLC/HDLC) Mode ................................................................................................... 4-19
4.4.1 SDLC Transmit ...........................................................................................................................................4-20
4.4.2 SDLC Receive ............................................................................................................................................4-24
4.4.3 SDLC Frame Status FIFO ...........................................................................................................................4-28
4.4.4 SDLC Loop Mode .......................................................................................................................................4-31
4.4.4.1 SDLC Loop Mode Receive .....................................................................................................................4-33
4.4.4.2 SDLC Loop Mode Transmit ..................................................................................... ,............................... 4-33
4.4.4.3 SDLC Loop Initialization ..........................................................................................................................4-34
Chapter 5
5.1 Introduction .............................................................................................................................................................5-1
5.2 Write Registers .......................................................................................................................................................5-2
5.2.1 Write Register 0 (Command Register) ...................................................................................................... 5-2
5.2.2 Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) ................................... 5-4
5.2.3 Write Register 2 (Interrupt Vector) ............................................................................................................ 5-7
5.2.4 Write Register 3 (Receive Parameters and Control) ................................................................................. 5-7
5.2.5 Write Register 4 (Transmit/Receive Miscellaneous Parameters and Modes) ........................................... 5-8
5.2.6 Write Register 5 (Transmit Parameters and Controls) ............................................................................. 5-10
5.2.8 Write Register 7 (Sync Character or SDLC Flag) .................................................................................... 5-11
5.2.7 Write Register 6 (Sync Characters or SDLC Address Field) ............................ :...................................... 5-11
5.2.9 Write Register 7 Prime (ESCC only) ......................................................................................;................. 5-12
5.2.10 Write Register 8 (Transmit Buffer) ........................................................................................................... 5-13
5.2.11 Write Register 9 (Master Interrupt Control) ............................................................................................. 5-13
5.2.12 Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) ..................................................... 5-14
5.2.13 Write Register 11 (Clock Mode Control) ................................................................................................. 5-16
5.2.14 Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) ................................................ 5-17
5.2.15 Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) ................................................ 5-18
5.2.16 Write Register 14 (Miscellaneous Control Bits) ....................................................................................... 5-18
5.2.17 Write Register 15 (External/Status Interrupt Control) .............................................................................. 5-20
5.3 Read Registers ..................................................................................................................................................... 5-21
5.3.1 Read Register 0 (Transmit/Receive Buffer Status and External Status) ................................................. 5-21
5.3.2 Read Register 1 ......................................................................................................................................5-23
5.3.3 Read Register 2 ......................................................................................................................................5-24
5.3.4 Read Register 3 ......................................................................................................................................5-25
5.3.5 Read Register 4 (ESCC Only) .................................................................................................................5-25
5.3.6 Read Register 5 (ESCC Only) .................................................................................................................5-25
5.3.7 Read Register 6 (Not on NMOS) ............................................................................................................. 5c25
5.3.8 Read Register 7 (Not on NMOS) ............................................................................................................. 5-25
5.3.9 Read Register 8 ......................................................................................................................................5-26
5.3.10 Read Register 9 (ESCC Only) .................................................................................................................5-26
5.3.11 Read Register 10 ....................................................................................................................................5-26
5.3.12 Read Register 11 (ESCC Only) ............................................................................................................... 5-26
5.3.13 Read Register 12 ....................................................................................................................................5-27
5.3.14 Read Register 13 ....................................................................................................................................5-27
5.3.15 Read Register 14 (ESCC Only) ............................................................................................................... 5-27
5.3.16 Read Register 15 ....................................................................................................................................5-27
iii
Chapter 6
6.1 Introduction ......................................................................................................................................................6-1
6.1.1 General ................................................................................................................................................... 6-1
6.2 Functional Descriptions ..........................................................................................................................................6-1
6.2.1 New Programmable WR7' (Write Register 7 Prime) ............................................................................. 6-1
6.2.2 Timing Improvements ........ ;................................................................................................................... 6-3
6.2.3 Other Improvements ..............................................................................................................................6-3
Application Notes
Interfacing Z80 CPUs to the Z8500 Perioheral Family ........................................................................................... 7-1
The Z180 Interfaced with the SCC at 10 MHz ...................................................................................................... 7-25
Using the Zilog Datacom Family with the 80186 CPU ......................................................................................... 7-59
SCC in Binary Synchronous Communications ..................................................................................................... 7c79
SCC (Serial Communication Controller) SDLC Mode of Operation ..................................................................... 7-89
Using SCC with Z8000 in SDLC Protocol .......................................................................................................... 7-101
Boost your System Performance using the Zilog ESCC .................................................................................... 7-113
Technical Considerations when Implementing LLAP ........................................................................................ 7-127
On-Chip Oscillator Design .................................................................................................................................7-149
Questions and Answers
SCC Questions and Answers .................................................................................................................................8-1
ESCC Questions and Answers ...............................................................................................................................8-5
SCC Support Products and Superintegration Devices
Z8S18000ZCO Product Spec ...............................................................................................................................9-1
Z8018100ZCO Product Spec ...............................................................................................................................9-2
Z8018101ZA6 Product Spec ...............................................................................................................................9-3
Z8018101ZCO Product Spec ...............................................................................................................................9-4
Z8523000ZCO Product Spec ...............................................................................................................................9-5
Z8018600ZCO Product Spec ...............................................................................................................................9-6
ZEPMDC00001 Product Spec ...............................................................................................................................9-7
ZEPMDC00002 Product Spec ................................................................................................................................ 9-8
SCC/ESCC Superintegration Devices
Z80181 ...................................................................................................................................................................9-9
Z80182 .................................................................................................................................................................9-10
iv
Figures
Chapter 1
Figure 1-1. SCC Block Diagram .......................................................................................................................... 1-4
Figure 1-2. Z85X30 Pin Functions ....................................................................................................................... 1-5
Figure 1-3. Z80X30 Pin Functions ....................................................................................................................... 1-6
[=igure 1-4. Z85X30 DIP Pin Assignments ........................................................................................................... 1-6
Figure 1-5. Z85X30 PLCC Pin Assignments ....................................................................................................... 1-6
Figure 1-6. Z80X30 DIP Pin Assignments ........................................................................................................... 1-7
Figure 1-7. Z80X30 PLCC Pin Assignments ....................................................................................................... 1-7
Chapter 2
Figure 2-1. Z80X30 Read Cycle ........................................................................................................................ 2-2
Figure 2-2. Z80X30 Write Cycle ......................................................................................................................... 2-3
Figure 2-3. Z80X30 Interrupt Acknowledge Cycle ............................................................................................ 2-4
Figure 2-4. Write Register 7 Prime (WR7') ......................................................................................................... 2-8
Figure 2-5. Z85X30 Read Cycle Timing ........................................................................................................... 2-10
Figure 2-6. Z85X30 Write Cycle Timing ........................................................................................................... 2-11
Figure 2-7. Z85X30 Interrupt Acknowledge Cycle Timing ............................................................................... 2-11
Figure 2-8. Write Register 7 Prime (WR7') ....................................................................................................... 2-14
Figure 2-9. ESCC Interrupt Sources ................................................................................................................ 2-16
Figure 2-11. Internal Priority Resolution ............................................................................................................. 2-17
Figure 2-10. Peripheral Interrupt Structure ........................................................................................................ 2-17
Figure 2-12. RR3 Interrupt Pending Bits ............................................................................................................ 2-18
Figure 2-13. Interrupt Flow Chart (for each interrupt source) ............................................................................ 2-20
Figure 2-14. Write Register 1 Receive Interrupt Mode Control .......................................................................... 2-22
Figure 2-15. Special Conditions Interrupt Service Flow .................................................................................... 2-24
Figure 2-16. TxlP Latching on the ESCC ........................................................................................................... 2-26
Figure 2-17. Operation of TBE, Tx Underrun/EOM and TxlP on NMOS/CMOS ................................................. 2-27
Figure 2-18. Operation of TBE, Tx Underrun/EOM and TxlP on ESCC ............................................................. 2-27
Figure 2-19. Flowchart example of processing an end of packet ..................................................................... 2-28
Figure 2-20. RRO External/Status Interrupt Operation ....................................................................................... 2-29
Figure 2-21. Wait On Transmit Timing ............................................................................................................... 2-32
Figure 2-22. Wait On Transmit Timing ............................................................................................................... 2-32
Figure 2-23. Wait On Receive Timing ................................................................................................................ 2-33
Figure 2-24. Wait On Receive Timing ................................................................................................................ 2-33
Figure 2-25. Transmit Request Assertion .......................................................................................................... 2-34
Figure 2-26. Z80X30 Transmit Request Release ............................................................................................... 2-35
Figure 2-27. Z85X30 Transmit Request Release ............................................................................................... 2-35
Figure 2-28. /DTR//REQ Deassertion Timing ..................................................................................................... 2-36
Figure 2-29. DMA Receive Request Assertion .................................................................................................. 2-37
Figure 2-30. Z80X30 Receive Request Release ................................................................................................ 2-38
Fig ure 2-31. Z85X30 Receive Request Release ................................................................................................ 2-38
Figure 2-32. Local Loopback ............................................................................................................................. 2-39
Figure 2-33. Auto Echo ......................................................................................................................................2-39
Chapter 3
Figure 3-1. Baud Rate Generator ........................................................................................................................ 3-1
Figure 3-2. Baud Rate Generator Start Up ......................................................................................................... 3-2
Figure 3-3. Data Encoding Methods ...................................................................................................................3-4
Figure 3-4. Manchester Encoding Circuit ........................................................................................................... 3-6
Figure 3-5. Digital Phase-Locked Loop .............................................................................................................. 3-7
Figure 3-6. DPLL in NRZI Mode ..........................................................................................................................3-8
Figure 3-7. DPLL Operating Example (NRZI Mode) ........................................................................................... 3-9
Figure 3-8. DPLL Operation in the FM Mode ...................................................................................................... 3-9
v
Figure 3-9. DPLL Transmit Clock Counter Output (ESCC only) ...................................................................... 3-11
Figure 3-10. Clock Multiplexer ........................................................................................................................... 3-13
Figure 3-11. Async Clock Setup Using an External Crystal ............................................................................... 3-13
Figure 3-12. Clock Source Selection ..................................................................................................................3-14
Figure 3-13. Synchronous Transmission, 1x Clock Rate, FM Data Encoding, using DPLL ............................... 3-14
Chapter 4
Figure 4-1. Transmit Data Path ..........................................................................................................................4-1
Figure 4-2 Receive Data Path ........................................................................................................................... 4-2
Figure 4-3. Asynchronous Message Format ...................................................................................................... 4-3
Figure 4-4. Monosync Data Character Format ..................................................................................................4-8
Figure 4-5. Sync Character Programming ....................................................................................................... 4-12
Figure 4-6. /SYNC as an Input ......................................................................................................................... 4-13
Figure 4-7. /SYNC as an Output ...................................................................................................................... 4-13
Figure 4-8. Changing Character Length .......................................................................................................... 4-14
Figure 4-9. Receive CRC Data Path ................................................................................................................ 4-15
Figure 4-10. Transmitter to Receiver Synchronization .......................................................................................4-18
Figure 4-11. SDLC Message Format ................................................................................................................. 4-19
Figure 4-12 /SYNC as an Output ...................................................................................................................... 4-24
Figure 4-13. Changing Character Length .......................................................................................................... 4-25
Figure 4-14. Residue Code 101 Interpretation .................................................................................................. 4-26
Figure 4-15. SDLC Frame Status FIFO (N/A on NMOS) .................................................................................... 4-29
Figure 4-16. SDLC Byte Counting Detail ........................................................................................................... 4-30
Chapter 5
Figure 5-1. Write Register 0 in the Z85X30 ........................................................................................................ 5-3
Figure 5-2. Write Register 0 in the Z80X30 ........................................................................................................ 5-3
Figure 5-3. Write Register 1 ...............................................................................................................................5-4
Figure 5-4. Write Register 2 ...............................................................................................................................5-7
Figure 5-5. Write Register 3 ...............................................................................................................................5-7
Figure 5-6. Write Register 4 ...............................................................................................................................5-8
Figure 5-7. Write Register 5 .............................................................................................................................5-10
Figure 5-9. Write Register 7 .............................................................................................................................5-11
Figure 5-8. Write Register 6 ............................................................................................................................. 5-11
Figure 5-10. Write Register 7 Prime ................................................................................................................... 5-12
Figure 5-11. Write Register 9 .............................................................................................................................5-13
Figure 5-12. Write Register 10 ...........................................................................................................................5-14
Figure 5-13. NRZ (NRZI), FM1 (FMO) Timing .....................................................................................................5-15
Figure 5-14. Write Register 11 ...........................................................................................................................5-16
Figure 5-15. Write Register 12 ...........................................................................................................................5-18
Figure 5-16. Write Register 13 ...........................................................................................................................5-18
Figure 5-17. Write Register 14 ...........................................................................................................................5-18
Figure 5-18. Write Register 15 ...........................................................................................................................5-20
Figure 5-19. Read Register 0 .............................................................................................................................5-21
Figure 5-20. Read Register 1 .............................................................................................................................5-23
Figure 5-21. Read Register 2 .............................................................................................................................5-24
Figure 5-22. Read Register 3 .............................................................................................................................5-25
Figure 5-23. Read Register 6 (Not on NMOS) ................................................................................................... 5-25
Figure 5-24. Read Register 7 (Not on NMOS) ................................................................................................... 5-25
Figure 5-25. Read Register 10 ...........................................................................................................................5-26
Figure 5-26. Read Reg ister 12 ...........................................................................................................................5-27
Figure 5-27. Read Register 13 ........................................................................................................................... 5-27
Figure 5-28. Read Register 15 ...........................................................................................................................5-27
vi
Tables
Chapter 2
Table 2-1. Z80X30 Register Map (Shift Left Mode) ............................................................................................. 2-6
Table 2-2. Z80X30 Register Map (Shift Right Mode) .......................................................................................... 2-7
Table 2-3. Z80230 SDLC/HDLC Enhancement Options ..................................................................................... 2-8
Table 2-4. Z80X30 Register Reset Values .......................................................................................................... 2-9
Table 2-5. Z85X30 Register Map ...................................................................................................................... 2-13
Table 2-7. Z85X30 Register Reset Values ........................................................................................................ 2-15
Table 2-8. Interrupt Source Priority ...................................................................................................................2-16
Table 2-9. Interrupt Vector Modification ........................................................................................................... 2-19
Chapter 3
Table 3-1. Baud Rates for 2.4576 MHz Clock and 16x Clock Factor ................................................................. 3-3
Chapter 4
Table 4-1. Write Register Bits Ignored in Asynchronous Mode .......................................................................... 4-4
Table 4-2. Transmit Bits per Character ............................................................................................................... 4-5
Table 4-3. Initialization Sequence Asynchronous Mode .................................................................................... .4-7
Table 4-4. Registers Used in Character-Oriented Modes .................................................................................. 4-9
Table 4-5. Transmitter Initialization in Character- Oriented Mode .................................................................... 4-11
Table 4-6. Sync Character Length Selection .................................................................................................... 4-12
Table 4-7. Enabling and Disabling CRC ...........................................................................................................4-17
Table 4-8. Initializing the Receiver in Character-Oriented Mode ...................................................................... 4-18
Table 4-9. ESCC Action Taken on Tx Underrun ............................................................................................... 4-21
Table 4-10. Residue Codes ................................................................................................................................4-26
Table 4-11. Initializing in SDLC Mode .................................................................................................................4-28
Table 4-12. SDLC Loop Mode Initialization ........................................................................................................ 4-34
Chapter 5
Table 5-1. SCC Write Registers ..........................................................................................................................5-1
Table 5-2. SCC Read Registers ..........................................................................................................................5-1
Table 5-3. Z85X30 Register Map ........................................................................................................................5-5
Table 5-4. Receive Bits per Character ................................................................................................................ 5-7
Table 5-5. Transmit Bits per Character ............................................................................................................. 5-10
Table 5-6. Interrupt Vector Modification ........................................................................................................... 5-13
Table 5-7. Data Encoding .................................................................................................................................5-14
Table 5-8. Receive Clock Source .....................................................................................................................5-17
Table 5-9. Transmit Clock Source .....................................................................................................................5-17
Table 5-10. Transmit External Control Selection ................................................................................................. 5-17
Table 5-11. I-Field Bit Selection (8 Bits Only) .....................................................................................................5-24
Table 5-12. Bits per Character Residue Decoding ............................................................................................. 5-24
Table 5-13. Read Register 7 FIFO Status Decoding .......................................................................................... 5-26
vii
~2iU]l.,
USER's MANUAL
CHAPTER 1
GENERAL DESCRIPTION
1.1 INTRODUCTION
The Zilog SCC Serial Communication Controller is a dual The SCC/ESCC family consists of the following seven
channel, multiprotocol data communication peripheral devices;
designed for use with 8- and 16-bit microprocessors. The
SCC functions as a serial-to-parallel, parallel-to-serial con- Z-Bus~ Universal-Bus
verter/controller. The SCC can be software-configured to NMOS Z8030 Z8530
satisfy a wide variety of serial communications applica- CMOS Z80C30 Z85C30
tions. The device contains a variety of new, sophisticated ESCC Z80230 Z85230
internal functions including on-chip baud rate generators, EMSCC Z85233
digital phase-lock loops, and crystal oscillators, which
dramatically reduce the need for external logic. As a convention, use the following words to distinguish the
devices throughout this document.
The SCC handles asynchronous formats, synchronous SCC: Description applies to all versions.
byte-oriented protocols such as IBM~ Bisync, and syn- NMOS: Description applies to NMOS version
chronous bit-oriented protocols such as HDLC and IBM (Z8030/Z8530)
SDLC. This versatile device supports virtually any serial CMOS: Description applies to CMOS version
data transfer application (telecommunication, LAN, etc.) (Z80C30/Z85C30)
ESCC: Description appliesto ESCC (Z80230/Z85230)
The device can generate and check CRC codes in any EMSCC: Description applies to EMSCC (Z85233)
synchronous mode and can be programmed to check Z80X30: Description applies to Z-Bus version of the
data integrity in various modes. The SCC also has facilities device (Z8030/Z80C30/Z80230)
for modem control in both channels. In applications where Z85X3X: Description applies to Universal version of the
these controls are not needed, the modem controls can be device (Z8530/Z85C30/Z85230/Z85233)
used for general-purpose I/O.
The Z-Bus version has a multiplexed bus interface and is
With access to 14 Write registers and 7 Read registers per directly compatible with the Z8000, Z16COO and 80x86
channel (the number of the registers varies depending on CPUs. The Universal version has a non-multiplexed bus
the version), the user can configure the SCC to handle all interface and easily interfaces with virtually any CPU,
synchronous formats regardless of data size, number of including the 8080, Z80, 68XOO. The 85C30 (SL 1480
stop bits, or parity requirements. Version) contains added SDLC enhancements which are
described in Chapter 6.
Within each operating mode, the SCC also allows for
protocol variations by checking odd or even parity bits,
character insertion or deletion, CRC generation, checking
break and abort generation and detection, and many other
protocol-dependent features.
1-1
1.2 SCC'S CAPABILITIES
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