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                                                                                                                              October 1997




     FDC6302P
     Digital FET, Dual P-Channel
     General Description                                                              Features
     These Dual P-Channel logic level enhancement mode field effect                     -25 V, -0.12 A continuous, -0.5 A Peak.
     transistors are produced using Fairchild's proprietary, high cell                             R DS(ON) = 13  @ VGS= -2.7 V
     density, DMOS technology. This very high density process is                                   R DS(ON) = 10  @ VGS = -4.5 V.
     especially tailored to minimize on-state resistance. This device
     has been designed especially for low voltage applications as a                     Very low level gate drive requirements allowing direct
     replacement for digital transistors in load switchimg applications.                operation in 3V circuits. VGS(th) < 1.5V.
     Since bias resistors are not required this one P-Channel FET
     can replace several digital transistors with different bias resistors              Gate-Source Zener for ESD ruggedness.
     like the IMBxA series.                                                             >6kV Human Body Model
                                                                                        Replace multiple PNP digital transistors (IMHxA series) with
                                                                                        one DMOS FET.




          SOT-23                   SuperSOTTM-6            SuperSOTTM-8                 SO-8                 SOT-223             SOIC-16




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 Absolute Maximum Ratings                         TA = 25oC unless other wise noted
Symbol         Parameter                                                                             FDC6302P                              Units
VDSS           Drain-Source Voltage                                                                        -25                               V
VGSS           Gate-Source Voltage                                                                         -8                                V
ID             Drain Current                 - Continuous                                               -0.12                                A
                                             - Pulsed                                                    -0.5
PD             Maximum Power Dissipation                         (Note 1a)                                 0.9                               W
                                                                 (Note 1b)                                 0.7
TJ,TSTG        Operating and Storage Temperature Range                                                -55 to 150                            

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