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                                                                                                                          June 2008




  FDG6322C
  Dual N & P Channel Digital FET
  General Description                                                                    Features

 These dual N & P-Channel logic level enhancement mode                                       N-Ch 0.22 A, 25 V, RDS(ON) = 4.0  @ VGS= 4.5 V,
 field effect transistors are produced using Fairchild's
                                                                                                            RDS(ON) = 5.0  @ VGS= 2.7 V.
 proprietary, high cell density, DMOS technology. This very
 high density process is especially tailored to minimize                                     P-Ch -0.41 A,-25V, RDS(ON) = 1.1  @ VGS= -4.5V,
 on-state resistance. This device has been designed
                                                                                                            RDS(ON) = 1.5  @ VGS= -2.7V.
 especially for low voltage applications as a replacement for
 bipolar digital transistors and small signal MOSFETs. Since                                 Very small package outline SC70-6.
 bias resistors are not required, this dual digital FET can
 replace several different digital transistors, with different bias                          Very low level gate drive requirements allowing direct
 resistor values.                                                                            operation in 3 V circuits (VGS(th) < 1.5 V).
                                                                                             Gate-Source Zener for ESD ruggedness
                                                                                             (>6kV Human Body Model).




         SC70-6                          SOT-23                    SuperSOTTM-6              SOT-8                    SO-8                   SOIC-14




                                               S2                                                        1                               6
                                        G2
                                                                                                                             Q1
                                  D1
                                                                                                         2                               5
                                                              D2                                                             Q2
                                       pin 1             G1
                                                    S1                                                   3                               4
                    SC70-6
                    Mark: .22




    Absolute Maximum Ratings                             TA = 25oC unless other wise noted
  Symbol          Parameter                                                                  N-Channel                       P-Channel            Units

  VDSS            Drain-Source Voltage                                                          25                                -25                  V

  VGSS            Gate-Source Voltage                                                            8                                -8                   V
  ID              Drain Current          - Continuous                                          0.22                            -0.41                   A
                                         - Pulsed                                              0.65                               -1.2
  PD              Maximum Power Dissipation                           (Note 1)                                  0.3                                    W
  TJ,TSTG         Operating and Storage Temperature Range                                                    -55 to 150                                

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