Service Manuals, User Guides, Schematic Diagrams or docs for : . Electronic Components Datasheets Active components Transistors Philips bf1100wr
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download bf1100wr documenatation <<
Text preview - extract from the document
DISCRETE SEMICONDUCTORS
DATA SHEET
BF1100WR
Dual-gate MOS-FET
Product specification 1995 Apr 25
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
FEATURES PINNING
Specially designed for use at 9 to 12 V supply voltage PIN SYMBOL DESCRIPTION
Short channel transistor with high forward transfer 1 s, b source
admittance to input capacitance ratio
2 d drain
Low noise gain controlled amplifier up to 1 GHz
3 g2 gate 2
Superior cross-modulation performance during AGC.
4 g1 gate 1
APPLICATIONS
VHF and UHF applications such as television tuners and handbook, halfpage d
professional communications equipment.
3 4
DESCRIPTION
g2
Enhancement type field-effect transistor in a plastic
g1
microminiature SOT343R package. The transistor
consists of an amplifier MOS-FET with source and
substrate interconnected and an internal bias circuit to 2 1
ensure good cross-modulation performance during AGC.
Top view MAM192 s,b
CAUTION
The device is supplied in an antistatic package. The Marking code: MF.
gate-source input must be protected against static
Fig.1 Simplified outline (SOT343R) and symbol.
discharge during transport or handling.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VDS drain-source voltage 14 V
ID drain current 30 mA
Ptot total power dissipation 280 mW
Tj operating junction temperature 150 C
yfs forward transfer admittance 24 28 33 mS
Cig1-s input capacitance at gate 1 2.2 2.6 pF
Crs reverse transfer capacitance f = 1 MHz 25 35 fF
F noise figure f = 800 MHz 2 dB
1995 Apr 25 2
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDS drain-source voltage 14 V
ID drain current 30 mA
IG1 gate 1 current 10 mA
IG2 gate 2 current 10 mA
Ptot total power dissipation see Fig.2; up to Tamb = 50 C; note 1 280 mW
Tstg storage temperature 65 +150 C
Tj operating junction temperature +150 C
Note
1. Device mounted on a printed-circuit board.
MLD180 MLD156
300 40
handbook, halfpage
Y fs
Ptot
(mS)
(mW)
30
200
20
100
10
0 0
0 50 100 150 200 50 0 50 100 150
Tamb ( oC) T j ( oC)
Fig.3 Forward transfer admittance as a function
Fig.2 Power derating curve. of junction temperature; typical values.
1995 Apr 25 3
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
THERMAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth j-a thermal resistance from junction to ambient note 1 350 K/W
Rth j-s thermal resistance from junction to soldering point Ts = 91 C; note 2 210 K/W
Notes
1. Device mounted on a printed-circuit board.
2. Ts is the temperature at the soldering point of the source lead.
STATIC CHARACTERISTICS
Tj = 25 C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
V(BR)G1-SS gate 1-source breakdown voltage VG2-S = VDS = 0; IG1-S = 1 mA 13.2 20 V
V(BR)G2-SS gate 2-source breakdown voltage VG1-S = VDS = 0; IG2-S = 1 mA 13.2 20 V
V(F)S-G1 forward source-gate 1 voltage VG2-S = VDS = 0; IS-G1 = 10 mA 0.5 1.5 V
V(F)S-G2 forward source-gate 2 voltage VG1-S = VDS = 0; IS-G2 = 10 mA 0.5 1.5 V
VG1-S(th) gate 1-source threshold voltage VG2-S = 4 V; VDS = 9 V; 0.3 1 V
ID = 20 A
VG2-S = 4 V; VDS = 12 V; 0.3 1 V
ID = 20 A
VG2-S(th) gate 2-source threshold voltage VG1-S = 4 V; VDS = 9 V; 0.3 1.2 V
ID = 20 A
VG1-S = 4 V; VDS = 12 V; 0.3 1.2 V
ID = 20 A
IDSX drain-source current VG2-S = 4 V; VDS = 9 V; 8 13 mA
RG1 = 180 k; note 1
VG2-S = 4 V; VDS = 12 V; 8 13 mA
RG1 = 250 k; note 2
IG1-SS gate 1 cut-off current VG2-S = VDS = 0; VG1-S = 12 V 50 nA
IG2-SS gate 2 cut-off current VG1-S = VDS = 0; VG2-S = 12 V 50 nA
Notes
1. RG1 connects gate 1 to VGG = 9 V; see Fig.26.
2. RG1 connects gate 1 to VGG = 12 V; see Fig.26.
1995 Apr 25 4
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
DYNAMIC CHARACTERISTICS
Common source; Tamb = 25 C; VG2-S = 4 V; ID = 10 mA; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
yfs forward transfer admittance pulsed; Tj = 25 C
VDS = 9 V 24 28 33 mS
VDS = 12 V 24 28 33 mS
Cig1-s input capacitance at gate 1 f = 1 MHz
VDS = 9 V 2.2 2.6 pF
VDS = 12 V 2.2 2.6 pF
Cig2-s input capacitance at gate 2 f = 1 MHz
VDS = 9 V 1.6 pF
VDS = 12 V 1.4 pF
Cos drain-source capacitance f = 1 MHz
VDS = 9 V 1.4 1.8 pF
VDS = 12 V 1.1 1.5 pF
Crs reverse transfer capacitance f = 1 MHz
VDS = 9 V 25 35 fF
VDS = 12 V 25 35 fF
F noise figure f = 800 MHz; GS = GSopt; BS = BSopt
VDS = 9 V 2 2.8 dB
VDS = 12 V 2 2.8 dB
MLD157 MLD158
0 120
handbook, halfpage handbook, halfpage
gain
Vunw
reduction
(dB) (dBV)
10 (1)
110
(2)
20
100
30
90
40
50 80
0 1 2 3 4 0 10 20 30 40 50
VAGC (V) gain reduction (dB)
(1) RG = 250 k to VGG = 12 V.
(2) RG = 180 k to VGG = 9 V.
f = 50 MHz. fw = 50 MHz; funw = 60 MHz; Tamb = 25 C.
Tj = 25 C.
Fig.5 Unwanted voltage for 1% cross-modulation
Fig.4 Gain reduction as a function of the AGC as a function of gain reduction; typical
voltage; typical values. values; see Fig.26.
1995 Apr 25 5
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
MLD159 MLD160
20 20
handbook, halfpage handbook, halfpage
ID V G1 S = 1.4 V ID V G2 S = 4 V 3 V 2.5 V
(mA) (mA)
2V
16 16
1.3 V
1.2 V
12 12
1.1 V 1.5 V
8 8
1.0 V
4 0.9 V
4
1V
0 0
0 4 8 12 16 0 0.4 0.8 1.2 1.6 2.0
V DS (V) V G1 S (V)
VG2-S = 4 V. VDS = 9 to 12 V.
Tj = 25 C. Tj = 25 C.
Fig.6 Output characteristics; typical values. Fig.7 Transfer characteristics; typical values.
MLD161 MLD162
250 40
handbook, halfpage handbook, halfpage
I G1 V G2 S = 4 V y fs
(A) V G2 S = 4 V
(mS)
200
3.5 V 30 3.5 V
3V
150 3V
20
100 2.5 V
2V 10
50 2.5 V
2V
0 0
0 1 2 3 0 10 20 30
V G1 S (V) I D (mA)
VDS = 9 to 12 V. VDS = 9 to 12 V.
Tj = 25 C. Tj = 25 C.
Fig.8 Gate 1 current as a function of gate 1 Fig.9 Forward transfer admittance as a function
voltage; typical values. of drain current; typical values.
1995 Apr 25 6
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
MLD163 MLD164
16 20
handbook, halfpage handbook, halfpage
R G1 = 100 k
ID ID
147 k
(mA) (mA)
12 15 180 k
205 k
249 k
8 10
301 k
402 k
511 k
4 5
0 0
0 20 40 60 80 0 4 8 12 16
I G1 (A) V GG = V DS (V)
VG2-S = 4 V.
VDS = 9 to 12 V. RG1 connected to VGG.
VG2-S = 4 V. Tj = 25 C.
Tj = 25 C.
Fig.11 Drain current as a function of gate 1 supply
Fig.10 Drain current as a function of gate 1 current; voltage (= VGG) and drain supply voltage;
typical values. typical values; see Fig.26.
MLD165 MLD166
12 12
handbook, halfpage handbook, halfpage
ID ID
(mA) (mA)
8 8
4 4
0 0
0 2 4 6 8 10 0 4 8 12
V GG (V) V GG (V)
VDS = 9 V; VG2-S = 4 V. VDS = 12 V; VG2-S = 4 V.
RG1 = 180 kconnected to VGG); Tj = 25 C. RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.12 Drain current as a function of gate 1 voltage Fig.13 Drain current as a function of gate 1 voltage
(= VGG); typical values; see Fig.26. (= VGG); typical values; see Fig.26.
1995 Apr 25 7
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
MLD167 MLD168
50 50
handbook, halfpage handbook, halfpage
I G1 I G1 V GG = 12 V
V GG = 9 V
(A) (A)
40 40 11 V
8V
10 V
7V 9V
30 30
8V
6V
7V
5V
20 20
4V
10 10
0 0
0 2 4 6 0 2 4 6
V G2 S (V) V G2 S (V)
VDS = 9 V. VDS = 12 V.
RG1 = 180 k (connected to VGG); Tj = 25 C. RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.14 Gate 1 current as a function of gate 2 voltage; Fig.15 Gate 1 current as a function of gate 2 voltage;
typical values. typical values.
MLD169 MLD170
16 16
handbook, halfpage handbook, halfpage
ID ID
(mA) (mA)
V GG = 9 V V GG = 12 V
12 12
8V 11 V
10 V
7V 9V
6V 8V
8 5V 8 7V
4V
4 4
0 0
0 2 4 6 0 2 4 6
V G2 S (V) V G2 S (V)
VDS = 9 V. VDS = 12 V.
RG1 = 180 k (connected to VGG); Tj = 25 C. RG1 = 250 k (connected to VGG); Tj = 25 C.
Fig.16 Drain current as a function of the gate 2 Fig.17 Drain current as a function of the gate 2
voltage; typical values; see Fig.26. voltage; typical values; see Fig.26.
1995 Apr 25 8
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
MLD181 MLD182
10 2
handbook, halfpage 10 3 10 3
y is y rs rs
(mS) (S) (deg)
rs
10 10 2 10 2
b is
y rs
1 10 10
g is
10 1 1 1
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 9 V; VG2 = 4 V. VDS = 9 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.18 Input admittance as a function of Fig.19 Reverse transfer admittance and phase as
frequency; typical values. a function of frequency; typical values.
MLD183 MLD184
10 2 10 2 10
handbook, halfpage
yos
y fs
y fs fs (mS)
(mS) bos
(deg)
1
10 fs 10
10 1
gos
1 1 10 2
10 102 10 3 10 102 f (MHz) 10 3
f (MHz)
VDS = 9 V; VG2 = 4 V. VDS = 9 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.20 Forward transfer admittance and phase as Fig.21 Output admittance as a function of
a function of frequency; typical values. frequency; typical values.
1995 Apr 25 9
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
MLD185 MLD186
10 2
handbook, halfpage
10 3 10 3
y is y rs rs
(mS) (S) (deg)
rs
10 10 2 10 2
b is
y rs
1 10 10
g is
10 1 1 1
10 102 f (MHz) 10 3 10 102 f (MHz) 10 3
VDS = 12 V; VG2 = 4 V. VDS = 12 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.22 Input admittance as a function of Fig.23 Reverse transfer admittance and phase as
frequency; typical values. a function of frequency; typical values.
MLD187 MLD188
10 2 10 2 10
handbook, halfpage
yos
y fs (mS)
y fs fs
(mS)
(deg) bos
1
10 fs 10
10 1
gos
1 1 10 2
10 102 10 3 10 102 f (MHz) 10 3
f (MHz)
VDS = 12 V; VG2 = 4 V. VDS = 12 V; VG2 = 4 V.
ID = 10 mA; Tamb = 25 C. ID = 10 mA; Tamb = 25 C.
Fig.24 Forward transfer admittance and phase as Fig.25 Output admittance as a function of
a function of frequency; typical values. frequency; typical values.
1995 Apr 25 10
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
VAGC
handbook, full pagewidth
R1
10 k C1
4.7 nF C3 12 pF
C2 L1 RL
DUT 50
450 nH
R GEN R2 4.7 nF C4
RG
50 50
4.7 nF
VI
VGG V DS MGC420
For VGG = VDS = 9 V, RG = 180 k.
For VGG = VDS = 12 V, RG = 250 k.
Fig.26 Cross-modulation test circuit.
1995 Apr 25 11
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
Table 1 Scattering parameters: VDS = 9 V; VG2-S = 4 V; ID = 10 mA
s11 s21 s12 s22
f
(MHz) MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(ratio) (deg) (ratio) (deg) (ratio) (deg) (ratio) (deg)
50 0.985 3.9 2.618 175.1 0.001 137.9 1.000 1.9
100 0.981 7.3 2.602 170.5 0.001 80.4 0.999 4.0
200 0.975 14.4 2.577 160.7 0.002 74.0 0.995 7.6
300 0.965 21.6 2.555 151.6 0.002 79.3 0.994 11.3
400 0.947 28.3 2.513 141.8 0.003 80.5 0.992 15.0
500 0.927 34.9 2.449 133.4 0.003 82.8 0.988 18.5
600 0.913 41.7 2.339 124.6 0.003 78.9 0.984 22.0
700 0.890 47.9 2.361 115.4 0.003 80.6 0.982 25.3
800 0.869 54.0 2.302 106.4 0.003 93.9 0.979 28.8
900 0.845 59.7 2.228 97.6 0.003 104.8 0.976 32.1
1000 0.823 65.4 2.167 89.6 0.003 129.3 0.974 35.5
Table 2 Noise data: VDS = 9 V; VG2-S = 4 V; ID = 10 mA
f Fmin opt
rn
(MHz) (dB) (ratio) (deg)
800 2.00 0.67 43.9 0.89
Table 3 Scattering parameters: VDS = 12 V; VG2-S = 4 V; ID = 10 mA
s11 s21 s12 s22
f
(MHz) MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE MAGNITUDE ANGLE
(ratio) (deg) (ratio) (deg) (ratio) (deg) (ratio) (deg)
50 0.985 3.7 2.576 175.3 0.000 125.0 1.000 1.6
100 0.980 7.4 2.563 170.9 0.001 111.2 1.000 3.3
200 0.973 14.6 2.541 161.6 0.002 83.0 0.997 6.4
300 0.962 21.5 2.519 152.9 0.002 85.2 0.996 9.3
400 0.946 28.5 2.479 143.5 0.003 79.4 0.995 12.4
500 0.929 35.0 2.419 135.5 0.003 78.2 0.991 15.3
600 0.912 41.6 2.373 127.2 0.003 80.0 0.989 18.1
700 0.895 47.8 2.336 118.7 0.003 83.4 0.987 20.9
800 0.868 53.8 2.284 110.0 0.003 91.3 0.985 23.7
900 0.845 59.8 2.213 101.6 0.003 95.9 0.983 26.5
1000 0.823 65.7 2.160 94.1 0.003 112.2 0.981 29.3
Table 4 Noise data: VDS = 12 V; VG2-S = 4 V; ID = 10 mA
f Fmin opt
rn
(MHz) (dB) (ratio) (deg)
800 2.00 0.66 43.3 0.97
1995 Apr 25 12
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
PACKAGE OUTLINE
Plastic surface-mounted package; reverse pinning; 4 leads SOT343R
D B E A X
y HE v M A
e
3 4
Q
A
A1
c
2 1
w M B bp b1 Lp
e1
detail X
0 1 2 mm
scale
DIMENSIONS (mm are the original dimensions)
A1
UNIT A bp b1 c D E e e1 HE Lp Q v w y
max
1.1 0.4 0.7 0.25 2.2 1.35 2.2 0.45 0.23
mm 0.1 1.3 1.15 0.2 0.2 0.1
0.8 0.3 0.5 0.10 1.8 1.15 2.0 0.15 0.13
OUTLINE REFERENCES EUROPEAN
ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION
97-05-21
SOT343R
06-03-16
1995 Apr 25 13
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
DATA SHEET STATUS
DOCUMENT PRODUCT
DEFINITION
STATUS(1) STATUS(2)
Objective data sheet Development This document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This document contains the product specification.
Notes
1. Please consult the most recently issued document before initiating or completing a design.
2. The product status of device(s) described in this document may have changed since this document was published
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DEFINITIONS Right to make changes NXP Semiconductors
reserves the right to make changes to information
Product specification The information and data
published in this document, including without limitation
provided in a Product data sheet shall define the
specifications and product descriptions, at any time and
specification of the product as agreed between NXP
without notice. This document supersedes and replaces all
Semiconductors and its customer, unless NXP
information supplied prior to the publication hereof.
Semiconductors and customer have explicitly agreed
otherwise in writing. In no event however, shall an Suitability for use NXP Semiconductors products are
agreement be valid in which the NXP Semiconductors not designed, authorized or warranted to be suitable for
product is deemed to offer functions and qualities beyond use in life support, life-critical or safety-critical systems or
those described in the Product data sheet. equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reasonably be
expected to result in personal injury, death or severe
DISCLAIMERS
property or environmental damage. NXP Semiconductors
Limited warranty and liability Information in this accepts no liability for inclusion and/or use of NXP
document is believed to be accurate and reliable. Semiconductors products in such equipment or
However, NXP Semiconductors does not give any applications and therefore such inclusion and/or use is at
representations or warranties, expressed or implied, as to the customer's own risk.
the accuracy or completeness of such information and
Applications Applications that are described herein for
shall have no liability for the consequences of use of such
any of these products are for illustrative purposes only.
information.
NXP Semiconductors makes no representation or
In no event shall NXP Semiconductors be liable for any warranty that such applications will be suitable for the
indirect, incidental, punitive, special or consequential specified use without further testing or modification.
damages (including - without limitation - lost profits, lost
Customers are responsible for the design and operation of
savings, business interruption, costs related to the
their applications and products using NXP
removal or replacement of any products or rework
Semiconductors products, and NXP Semiconductors
charges) whether or not such damages are based on tort
accepts no liability for any assistance with applications or
(including negligence), warranty, breach of contract or any
customer product design. It is customer's sole
other legal theory.
responsibility to determine whether the NXP
Notwithstanding any damages that customer might incur Semiconductors product is suitable and fit for the
for any reason whatsoever, NXP Semiconductors' customer's applications and products planned, as well as
aggregate and cumulative liability towards customer for for the planned application and use of customer's third
the products described herein shall be limited in party customer(s). Customers should provide appropriate
accordance with the Terms and conditions of commercial design and operating safeguards to minimize the risks
sale of NXP Semiconductors. associated with their applications and products.
1995 Apr 25 14
NXP Semiconductors Product specification
Dual-gate MOS-FET BF1100WR
NXP Semiconductors does not accept any liability related Export control This document as well as the item(s)
to any default, damage, costs or problem which is based described herein may be subject to export control
on any weakness or default in the customer's applications regulations. Export might require a prior authorization from
or products, or the application or use by customer's third national authorities.
party customer(s). Customer is responsible for doing all
Quick reference data The Quick reference data is an
necessary testing for the customer's applications and
extract of the product data given in the Limiting values and
products using NXP Semiconductors products in order to
Characteristics sections of this document, and as such is
avoid a default of the applications and the products or of
not complete, exhaustive or legally binding.
the application or use by customer's third party
customer(s). NXP does not accept any liability in this Non-automotive qualified products Unless this data
respect. sheet expressly states that this specific NXP
Semiconductors product is automotive qualified, the
Limiting values Stress above one or more limiting
product is not suitable for automotive use. It is neither
values (as defined in the Absolute Maximum Ratings
qualified nor tested in accordance with automotive testing
System of IEC 60134) will cause permanent damage to
or application requirements. NXP Semiconductors accepts
the device. Limiting values are stress ratings only and
no liability for inclusion and/or use of non-automotive
(proper) operation of the device at these or any other
qualified products in automotive equipment or
conditions above those given in the Recommended
applications.
operating conditions section (if present) or the
Characteristics sections of this document is not warranted. In the event that customer uses the product for design-in
Constant or repeated exposure to limiting values will and use in automotive applications to automotive
permanently and irreversibly affect the quality and specifications and standards, customer (a) shall use the
reliability of the device. product without NXP Semiconductors' warranty of the
product for such automotive applications, use and
Terms and conditions of commercial sale NXP
specifications, and (b) whenever customer uses the
Semiconductors products are sold subject to the general
product for automotive applications beyond NXP
terms and conditions of commercial sale, as published at
Semiconductors' specifications such use shall be solely at
http://www.nxp.com/profile/terms, unless otherwise
customer's own risk, and (c) customer fully indemnifies
agreed in a valid written individual agreement. In case an
NXP Semiconductors for any liability, damages or failed
individual agreement is concluded only the terms and
product claims resulting from customer design and use of
conditions of the respective agreement shall apply. NXP
the product for automotive applications beyond NXP
Semiconductors hereby expressly objects to applying the
Semiconductors' standard warranty and NXP
customer's general terms and conditions with regard to the
Semiconductors' product specifications.
purchase of NXP Semiconductors products by customer.
No offer to sell or license Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyance or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
1995 Apr 25 15
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimers. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Contact information
For additional information please visit: http://www.nxp.com
For sales offices addresses send e-mail to: [email protected]
◦ Jabse Service Manual Search 2026 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo