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Philips Semiconductors                                                                           Objective specification

PowerMOS transistor                                                                                   PHP2N40E


GENERAL DESCRIPTION                       QUICK REFERENCE DATA
N-channel enhancement mode                 SYMBOL      PARAMETER                                     MAX.      UNIT
field-effect power transistor in a
plastic envelope featuring high            VDS         Drain-source voltage                           400        V
avalanche energy capability, stable        ID          Drain current (DC)                             2.5        A
blocking voltage, fast switching and       Ptot        Total power dissipation                         50        W
high thermal cycling performance           RDS(ON)     Drain-source on-state resistance               3.5        
with low thermal resistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.

PINNING - TO220AB                         PIN CONFIGURATION                    SYMBOL
  PIN            DESCRIPTION                                                                          d
                                                      tab

    1    gate

    2    drain
                                                                                           g
    3    source
  tab    drain
                                                            1 23                                      s


LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
 SYMBOL PARAMETER                           CONDITIONS                                    MIN.       MAX.      UNIT
 VDS        Drain-source voltage                                                           -          400        V
 VDGR       Drain-gate voltage              RGS = 20 k                                     -          400        V
 

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