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Philips Semiconductors                                                                                  Product specification

PowerMOS transistor                                                                                             PHP3N20L
Logic level FET

GENERAL DESCRIPTION                           QUICK REFERENCE DATA
N-channel enhancement mode logic               SYMBOL        PARAMETER                                      MAX.        UNIT
level field-effect power transistor in a
plastic envelope featuring high                VDS           Drain-source voltage                               200       V
avalanche energy capability, stable            ID            Drain current (DC)                                 3.5       A
blocking voltage, fast switching and           Ptot          Total power dissipation                             50       W
high thermal cycling performance               RDS(ON)       Drain-source on-state resistance                   1.5       
with low thermal resistance. Intended
for use in Switched Mode Power
Supplies (SMPS), motor control
circuits and general purpose
switching applications.

PINNING - TO220AB                             PIN CONFIGURATION                      SYMBOL
  PIN               DESCRIPTION                                                                                 d
                                                            tab

       1    gate

       2    drain
                                                                                                  g
       3    source
   tab      drain
                                                                  1 23                                          s


LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
 SYMBOL PARAMETER                               CONDITIONS                                       MIN.       MAX.        UNIT
 ID            Continuous drain current         Tmb = 25 

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