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A25L040 Series
4Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
Document Title
4Mbit, Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors
Revision History
Rev. No. History Issue Date Remark
1.0 Initial issue April 10, 2009 Final
1.1 Add packing description in Part Numbering Scheme May 3, 2010
1.2 P28: Change Data Retention and Endurance value from Max. October 20, 2010
to Min.
(October, 2010, Version 1.2) AMIC Technology Corp.
A25L040 Series
4Mbit Low Voltage, Serial Flash Memory
With 100MHz Uniform 4KB Sectors
FEATURES
Family of Serial Flash Memories Electronic Signatures
- A25L040: 4M-bit /512K-byte - JEDEC Standard Two-Byte Signature
Flexible Sector Architecture with 4KB sectors A25L040: (3013h)
- Sector Erase (4K-bytes) in 0.2s (typical) - RES Instruction, One-Byte, Signature, for backward
- Block Erase (64K-bytes) in 0.5s (typical) compatibility
Page Program (up to 256 Bytes) in 2ms (typical) A25L040 (12h)
2.7 to 3.6V Single Supply Voltage Package options
SPI Bus Compatible Serial Interface - 8-pin SOP (150/209mil), 8-pin DIP (300mil)
100MHz Clock Rate (maximum) - All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L040 are 4M bit Serial Flash Memory, with advanced sectors. Each sector is composed of 16 pages. Each page is
write protection mechanisms, accessed by a high speed 256 bytes wide. Thus, the whole memory can be viewed as
SPI-compatible bus. consisting of 2048 pages, or 524,288 bytes.
The memory can be programmed 1 to 256 bytes at a time, The whole memory can be erased using the Chip Erase
using the Page Program instruction. instruction, a block at a time, using Block Erase instruction, or a
sector at a time, using the Sector Erase instruction.
The memory is organized as 8 blocks, each containing 16
Pin Configurations
SOP8 Connections DIP8 Connections
A25L040 A25L040
S 1 8 VCC S 1 8 VCC
DO DO 2 7 HOLD
2 7 HOLD
W 3 6 C W 3 6 C
VSS VSS 4 5 DIO
4 5 DIO
(October, 2010, Version 1.2) 1 AMIC Technology Corp.
A25L040 Series
Block Diagram
HOLD
High Voltage
W Control Logic
Generator
S
C
DIO
I/O Shift Register
DO
Address register 256 Byte Status
and Counter Data Buffer Register
7FFFFh (4M)
Size of the
Y Decoder
memory area
00000h 000FFh
256 Byte (Page Size)
X Decoder
Pin Descriptions Logic Symbol
Pin No. Description
VCC
C Serial Clock
DIO Serial Data Input 1
DIO DO
DO Serial Data Output 2
C
S Chip Select
S A25L040
W Write Protect W
Hold HOLD
HOLD
VCC Supply Voltage
VSS
VSS Ground
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast
Read Dual Input-Output instruction is executed.
(October, 2010, Version 1.2) 2 AMIC Technology Corp.
A25L040 Series
SIGNAL DESCRIPTION impedance. Unless an internal Program, Erase or Write
Status Register cycle is in progress, the device will be in the
Serial Data Output (DO). This output signal is used to Standby mode (this is not the Deep Power-down mode).
transfer data serially out of the device. Data is shifted out on
Driving Chip Select ( S ) Low enables the device, placing it in
the falling edge of Serial Clock (C).
The DO pin is also used as an input pin when the Fast Read the active power mode.
Dual Input-Output instruction is executed. After Power-up, a falling edge on Chip Select ( S ) is required
Serial Data Input (DIO). This input signal is used to transfer prior to the start of any instruction.
data serially into the device. It receives instructions, Hold ( HOLD ). The Hold ( HOLD ) signal is used to pause
addresses, and the data to be programmed. Values are any serial communications with the device without
latched on the rising edge of Serial Clock (C).
deselecting the device.
The DIO pin is also used as an output pin when the Fast
During the Hold condition, the Serial Data Output (DO) is
Read Dual Output instruction and the Fast Read Dual
high impedance, and Serial Data Input (DIO) and Serial
Input-Output instruction are executed.
Serial Clock (C). This input signal provides the timing of the Clock (C) are Don't Care. To start the Hold condition, the
serial interface. Instructions, addresses, or data present at device must be selected, with Chip Select ( S ) driven Low.
Serial Data Input (DIO) are latched on the rising edge of Write Protect ( W ). The main purpose of this input signal is
Serial Clock (C). Data on Serial Data Output (DO) changes to freeze the size of the area of memory that is protected
after the falling edge of Serial Clock (C). against program or erase instructions (as specified by the
Chip Select ( S ). When this input signal is High, the device values in the BP2, BP1, and BP0 bits of the Status Register).
is deselected and Serial Data Output (DO) is at high
(October, 2010, Version 1.2) 3 AMIC Technology Corp.
A25L040 Series
SPI MODES
These devices can be driven by a microcontroller with its SPI falling edge of Serial Clock (C).
peripheral running in either of the two following modes: The difference between the two modes, as shown in Figure 2,
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