Service Manuals, User Guides, Schematic Diagrams or docs for : . Electronic Components Datasheets Various datasheets 74173
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download 74173 documenatation <<
Text preview - extract from the document
54173 DM54173 DM74173 TRI-STATE Quad D Registers
June 1989
54173 DM54173 DM74173
TRI-STATE Quad D Registers
General Description
These four-bit registers contain D-type flip-flops with totem- To minimize the possibility that two outputs will attempt to
pole TRI-STATE outputs capable of driving highly capaci- take a common bus to opposite logic levels the output con-
tive or low-impedance loads The high-impedance state and trol circuitry is designed so that the average output disable
increased high-logic-level drive provide these flip-flops with times are shorter than the average output enable times
the capability of driving the bus lines in a bus-organized sys-
tem without need for interface or pull-up components Features
Gated enable inputs are provided for controlling the entry of Y TRI-STATE outputs interface directly with system bus
data into the flip-flops When both data-enable inputs are Y Gated output control lines for enabling or disabling the
low data at the D inputs are loaded into their respective flip- outputs
flops on the next positive transition of the buffered clock Y Fully independent clock elminates restrictions for oper-
input Gate output control inputs are also provided When ating in one of two modes
both are low the normal logic states of the four outputs are Parallel load
available for driving the loads or bus lines The outputs are Do nothing (hold)
disabled independently from the level of the clock by a high Y For application as bus buffer registers
logic level at either output control input The outputs then Y Typical propagation delay 18 ns
present a high impedance and neither load nor drive the bus
line Detailed operation is given in the function table
Y Typical frequency 30 MHz
Y Typical power dissipation 250 mW
Y Alternate Military Aerospace device (54173) is avail-
able Contact a National Semiconductor Sales Office
Distributor for specifications
Connection Diagram Function Table
Dual-In-Line Package
Inputs
Output
Data Enable Data
Clear Clock Q
G1 G2 D
H X X X X L
L L X X X Q0
L u H X X Q0
L u X H X Q0
L u L L L L
L u L L H H
When either M or N (or both) is (are) high the output is disabled to the
high-impedance state however sequential operation of the flip-flops is
not affected
H e high level (steady state)
L e low level (steady state)
u e low-to-high level transition
X e don't care (any input including transitions)
Q0 e the level of Q before the indicated steady state input conditions were
established
TL F 6556 ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo