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Design & Evaluation of a Metrology Class, Delta-Sigma Analogue to Digital Converter
for the LHC project at CERN.
Allan Belcher1, John Pett2 & John Pickering3
1
Signal Conversion Ltd, Swansea, UK 2SL Group, CERN, Geneva, Switzerland
3
Metron Designs Ltd, Norwich, UK
1 Introduction
The new LHC (Large Hadron Collider) particle accelerator, currently under construction at CERN, Geneva, will
employ some 1700 converters powering cryogenic magnets to steer twin beams around the 27km ring. The
critical positioning of the beams is dynamically controlled by adjusting the magnet current from near zero to
some 13kAmps to track a pre-determined current profile to within a few parts per million (ppm).
The control is performed in a digital loop requiring A-D conversion capable of sub ppm performance at real
independent data rates up to the kHz region. Since no commercial product was available to meet this
requirement, especially in the anticipated working environment, one of us (John Pett) designed and developed an
a-d converter using Delta-Sigma technology. When prototypes became available, CERN sought independent
verification of its performance, by asking the other two of us, as "industry experts" to perform rigorous
evaluation of its operation and key parameters.
This paper outlines the CERN requirement as it relates to the A-D and describes at a functional level its
operational characteristics and shows how simulation can verify its time domain characteristics. DC and
Dynamic testing methods are described, along with the very difficult measurement source requirements. Finally
an outline of the results is presented revealing that this converter technology, more often associated with digital
audio, is quite capable of meeting very stringent metrology requirements.
2 Basic A-D Delta-Sigma Design
The ADC employed in the digital regulation loops for LHC is described in [1]. The choice of Delta-Sigma as the
conversion technology was, as far as was known at that time, the first time it had been utilised for very high
performance DC & LF metrology application. Such applications had previously turned exclusively to DVM-like
methods but in this case would not achieve the necessary resolution-bandwidth product to be useable in the
LHC's proposed magnet current digital control loops.
The basic structure chosen is shown in
Fig. 1. After a number of prototype 1 MHz
realisations were made, based on an CLK
initial optimisation of parameters buffer 3 integrators comparator
obtained via simulation, a third order input
LOGIC
integrator and 4th order digital filter
were selected as having the required "1-bit" output
performance with limited complexity. pulse stream
1 bit via fibre-
Furthermore a 1MHz clock was chosen DAC optic link
and each of the "sync 4" digital filter
Digital output
registers selected to be of 250 elements REF. Filter value
in length. This means that the filter (FPGA)
completely flushes through in 4X250 Fig 1
clocks or, in this case, 1 millisecond
giving a true complete conversion rate
of 1kHz.
3 Evaluating the Suitability and Capability of the Design
For a converter of this nature, intended to work to the required performance over a wide range of measurement
stimuli and conditions, it is virtually impossible to perform 100% testing and it is therefore necessary to
interpolate between sample measurements and therefore to have knowledge of the converter's characteristics in
order to validate the interpolations. Traditionally, charge balance A-Ds have been the technology of choice for
very high resolution DC measurements and are used in most high end DVMs. At first sight one would assume
that Delta-Sigma is a version of charge balance and would have the same speed:resolution characteristics, but if
it is viewed in that way it is clear that with a 1MHz clock and only 1000 1 bit samples the resolution cannot be
better than .1% (10 bits) where actual performance was expected to be around 22 bits. Delta-Sigma analysis in
the frequency domain can explain this
Clock, CL SUM1 conundrum but in this time domain
Array L stages
V1 (Vin) Vc1 +Vref (FS=L) application we felt it was necessary to
V3 Vf
V2 gain confidence in the actual
Vf -Vref SUM2 characteristics through analysis and
Array L stages
Vc2
(FS=L ) operation of a number of simulation 2
Vc3 Make Vc1/2 models.
for minimum
idle tones SUM3
Array L stages
(FS=L3)
Fig. 2 shows one of our simple models, a
Note:
VC1(n)=VC1(n-1)+.15*(V1-Vf) SUM4 simulation schematic that was
VC2(n)=VC2(n-1)+.15*VC1(n) Array L stages
V2(n) =VC2(n)+VC1(n)
(FS=L4) implemented in Excel. In order to more
VC3(n)=VC3(n-1)+.15*V2(n)
OUT
easily see what is happening within its
V3(n) =V2(n)+VC3(n)
Divide by: (FS=1) integrators and registers it was designed
FIG 2: Simulation "schematic" L*L*L*L to fully convert in only 200 clocks (L=50
in fig. 1) such that with true charge
balance, for example dual slope, it
would only have been able to 1 bit Delta-Sigma 3rd order 4X50 filter settling
achieve 0.5% resolution. The (Equivalent Charge Balance Resolution 0.5%)
sum2
results of a simple simulation are 0.77
sum3
shown in Fig 3 where the outputs Note fine resolution of sum4
sum4: Output
relative to 1 part in 200 !!
of the Sum2, Sum3 and Sum4 are
Value for each sum out register (detail)
input value
0.768
plotted against clock increment
from the start of the measurement
of an arbitrary value, in this case 0.766
.765432 of Full Scale. Quite clearly
the output (sum4) is settled and 0.764
within about .005% of the input
after only 200 clocks. To those
familiar with charge balance this is 0.762
quite extraordinary and indicates
that at the end of the measurement 0.76
period the net Reference charge
71
81
86
96
76
91
1
6
6
1
1
6
6
6
1
1
6
6
1
1
1
6
1
1
6
1
6
6
10
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entering the first integrator does Fig 3 clock# (last 130 of 200)
NOT equal the net Signal charge.
However, the third order integrator output responds to the second and third differentials of the signal and
reference waveforms giving it the necessary information for the digital filter to interpolate to the correct output
value. For a rigid analysis (in the frequency domain) see [2].
4k Out
4 Test Overview In 3k
DC testing and circuit design analysis were performed to ensure
linearity, stability, and overload requirements were met. Since
there was not an application need to cope with high slew rates the
dynamic testing was performed in the frequency domain using
7.32k 1.82k
10Hz-34Hz very pure sine wave signals whilst taking very long
data records at the converter's 1kHz output rate. This data was
analysed in special purpose "SATs" software [3] in order that the
A-D converter's dynamic performance could be presented in 8 Pole 20Hz
commonly used specification parameters such as Effective Number Active Filter,~
of Bits (ENOB). SATS uses algorithms that conform to present -50dB @ 68Hz
IEC standards and also incorporate recommendations of emerging 3.32k 909R
IEC standards [IEEE1241 and DYNAD].
All Caps
Whilst adequate DC calibration equipment exists to reach these 4.7uF
Polypropelyne
performance levels there is a significant problem for AC testing in
finding sources with low enough distortion to be distinguished
from that generated by the Device Under Test (DUT). We wanted
something greater than -120dB for harmonics of a 34 Hz 1.02k 1.02k
fundamental and excellent frequency stability over long data
acquisition periods. In the event we chose a simple digital function
generator, the HP33120A which for 30Hz signals had 2nd and 3rd Fig 4
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