Service Manuals, User Guides, Schematic Diagrams or docs for : . Rare and Ancient Equipment SOLARTRON 7081 Mickle diagrams 6264 (ws)
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High Speed Super Low Power SRAM
8K-Word By 8 Bit WS6264
GENERAL DESCRIPTION
The WS6264 is a high performance, high speed and super low power CMOS Static Random
Access Memory organized as 8,192 words by 8bits and operates from a single 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high speed, super low power features and
maximum access time of 70ns in 5.0V operation. Easy memory expansion is provided by using two chip
enable inputs (/CE1, CE2) and active LOW output enable (/OE).
The WS6264 has an automatic power down feature, reducing the power consumption significantly
when chip is deselected. The WS6264 is available in JEDEC standard 28-pin SOP(300 mil) and PDIP
(600 mil) packages.
FEATURES
Operation voltage : 4.5 ~ 5.5V
Ultra low power consumption:
Operating current 1mA@1MHz & CMOS standby current 1.0uA (Typ.) in Vcc=5.0V
High speed access time: 70ns.
Automatic power down when chip is deselected.
Three state outputs and TTL compatible.
Data retention supply voltage as low as 2.0V.
Easy expansion with /CE1, CE2 and /OE options.
PRODUCT FAMILY
Standby Current (Typ.)
Product Family Operating Temp. Vcc Range Speed (ns) Package Type
ICCSB1
WS6264LLFP 28 SOP
0~70oC 70 1.0uA
WS6264LLP 4.5~5.5V 28 PDIP
WS6264LLFPI
o
28 SOP
-40~85 C 70 1.0uA
WS6264LLPI 28 PDIP
Rev. 1.0
1
High Speed Super Low Power SRAM
8K-Word By 8 Bit WS6264
PIN CONFIGURATIONS
NC 1 28 VCC
A12 2 27 WE
A7 3 26 CE2
A6 4 25 A8
A5 5 24 A9
A4 6 23 A11
A3 7 28L SOP 22 OE
A2 8 28L PDIP 21 A10
A1 9 20 CE1
A0 10 19 DQ7
DQ0 11 18 DQ6
DQ1 12 17 DQ5
DQ2 13 16 DQ4
GND 14 15 DQ3
FUNCTIONAL BLOCK DIAGRAM
128 x512
Rev. 1.0
2
High Speed Super Low Power SRAM
8K-Word By 8 Bit WS6264
PIN DESCRIPTIONS
Name Type Function
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