Service Manuals, User Guides, Schematic Diagrams or docs for : . Rare and Ancient Equipment Wistron Motherboard Материнская плата Wistron Homa (TM15) wistron_homa_tm15_r1.0_schematics
<< Back | HomeMost service manuals and schematics are PDF files, so You will need Adobre Acrobat Reader to view : Acrobat Download Some of the files are DjVu format. Readers and resources available here : DjVu Resources
For the compressed files, most common are zip and rar. Please, extract files with Your favorite compression software ( WinZip, WinRAR ... ) before viewing. If a document has multiple parts, You should download all, before extracting.
Good luck. Repair on Your own risk. Make sure You know what You are doing.
Image preview - the first page of the document
>> Download wistron_homa_tm15_r1.0_schematics documenatation <<
Text preview - extract from the document
5 4 3 2 1
SYSTEM DC/DC
Homa (TM15") Block Diagram
Project code: 91.4Z401.001 TPS51125 49
PCB P/N : 48.4Z401.011 INPUTS OUTPUTS
REVISION : 07245-1
5V_S5(7A)
PCB STACKUP DCBATOUT
3D3V_S5(7A)
D CLK GEN. Mobile CPU TOP
D
ICS 9LPRS365 Penryn EMC2102 VCC
25 SYSTEM DC/DC
3 S TPS51124 51
4, 5 S INPUTS OUTPUTS
CRT CRT GND
HOST BUS 667/800/[email protected] 19 1D05V_S0(16A)
DCBATOUT
BOTTOM 1D8V_S3(16A)
DDR2 667/800MHz
Cantiga LCD
16 TPS51100 50
667/800 MHz
12,13 AGTL+ CPU I/F DDR_VREF_S3
5V_S5
DDR Memory I/F HDMI DVI
(1.5A)
DDR_VREF_S3_1
56
Port Replicator
DDR2 667/800MHz
INTEGRATED GRAHPICS
LVDS, CRT I/F PCIex16 G9131
667/800 MHz
12,13 6,7,8,9,10,11 VGA Borad 3D3V_S0 2D5V_S0
C X4 DMI 34
(300mA)
C
C-Link0
400MHz APL5912 50
Line In MS/MS Pro/xD 1D8V_S3 1D5V_S0
RealTek AZALIA
ICH9M Cardbus /MMC/SD
5 in 1
(2.5A)
41 31 CHARGER
6 PCIe ports OZ711MZ PCMCIA
ALC268 PCI BQ24750 53
PCI/PCI BRIDGE 36 SLOT 37
39 ACPI 2.0 INPUTS OUTPUTS
MIC In 4 SATA LAN
Giga LAN TXFM RJ45 RJ45 CHG_PWR
41 12 USB 2.0/1.1 ports 33 33
BCM5764M 32 18V 6.0A
ETHERNET (10/100/1000MbE) DCBATOUT
UP+5V
5V 100mA
High Definition Audio PWR SW
41 OP AMP LPC I/F
New card
G1412 35 TPS223135
Serial Peripheral I/F CPU DC/DC
Line Out 40 PCIex1 ISL6266A
Matrix Storage Technology(DO) Mini Card 48
B (No-SPDIF) Active Managemnet Technology(DO) Kedron a/b/g/n 38
B
INPUTS OUTPUTS
C Link1
OP AMP Mini Card VCC_CORE_S0
41 Kedron a/b/g/n 38 DCBATOUT
G1454 40 0~1.3V
LPC BUS 38A
INT.SPKR
20,21,22,23
USBX4 GFX DC/DC
MODEM BIOS HP OUT ISL6263
USB 48
RJ11 MDC Card SATA KBC Winbond
W25X80
LPC MIC IN
28 Winbond 43 DEBUG LINE IN INPUTS OUTPUTS
Mini USB Camera
WPC775 CONN.43
Blue Tooth 27 42 DCBATOUT
VCC_CORE_S0
HDD SATA Launch 0~1.3V
26 Buttom 5.5A
14
Finger USB
ODD SATA Printer 57 4 Port 29 Touch INT.
A 25 Pad 42 KB 42 970 A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
Homa -1
Date: Thursday, April 03, 2008 Sheet 1 of 57
5 4 3 2 1
A B C D E
ICH9M Integrated Pull-up Cantiga chipset and ICH9M I/O controller
ICH9M Functional Strap Definitions Rev.1.5 page 92 Hub strapping configuration
ICH9 EDS 642879 and Pull-down Resistors Montevina Platform Design guide 22339
page 218
0.5
Signal Usage/When Sampled Comment ICH9 EDS 642879 Rev.1.5 page 97
HDA_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 Pin Name Strap Description Configuration
PCIE Port Config 1bit1, pulled low.When TP3 not pulled low at rising edge SIGNAL Resistor Type/Value
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: CL_CLK[1:0] PULL-UP 20K CFG[2:0] FSB Frequency 000 = FSB1066
offset 224h). This signal has weak internal pull-down Select 011 = FSB667
CL_DATA[1:0] PULL-UP 20K 010 = FSB800
others = Reserved
4 HDA_SYNC PCIE config 1 bit 0,
Rising Edge of PWROK.
This signal has a weak internal pull-down.
Sets bit0 of RPC.PC(Config Registers:Offset 224h)
CL_RST0# PULL-UP 10K
CFG[4:3] Reserved
4
DPRSLPVR/GPIO16 PULL-DOWN 20K CFG8
GNT2#/ PCIE config2 bit2, This signal has a weak internal pull-up. CFG[15:14]
GPIO53 Rising Edge of PWROK. Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) ENERGY_DETECT PULL-UP 20K CFG[18:17]
GPIO20 Reserved, Rising Edge This signal has a weak internal pull-down. HDA_BIT_CLK PULL-DOWN 20K
of PWROK. This signal should not be pulled high. CFG5 DMI x2 Select 0 = DMI x2
HDA_DOCK_EN#/GPIO33 PULL-UP 20K 1 = DMI x4 (Default)
Tying this strap low configures DMI for ESI- CFG6 iTPM Host 0= The iTPM Host Interface is enabled(Note2)
compatible operation. This signal has a weak HDA_RST# PULL-DOWN 20K Interface 1=The iTPM Host Interface is disalbed(default)
GNT1#/ ESI Strap (Server Only) internal pull up. ESI compatible mode is for
GPIO51 Rising Edge of PWROK server platforms only.This signal should not HDA_SDIN[3:0] PULL-DOWN 20K 0 = Transport Layer Security (TLS) cipher
CFG7 Intel Management suite with no confidentiality
be pulled low for desttop and mobile. HDA_SDOUT PULL-DOWN 20K engine Crypto strap
1 = TLS cipher suite with
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for HDA_SYNC PULL-DOWN 20K confidentiality (default)
GNT3#/ Swap Override. all cycles targeting FWH BIOS space). 0 = Reverse Lanes,15->0,14->1 ect..
GPIO55 GLAN_DOCK# The pull-up or pull-down active when configured for nativeCFG9 PCIE Graphics Lane 1= Normal operation(Default):Lane
Rising Edge of PWROK. Note: Software will not be able to clear the GLAN_DOCK# functionality and determined by LAN controller
Top-Swap bit until the system is rebooted Numbered in order
GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K
without GNT3# being pulled down. 0 = Enable (Note 3)
GPIO[20] PULL-DOWN 20K CFG10 PCIE Loopback enable 1= Disabled (default)
GNT0#: Boot BIOS Destination Controllable via Boot BIOS Destination bit
SPI_CS1#/ Selection 0:1. (Config Registers:Offset 3410h:bit 11:10). GPIO[49] PULL-UP 20K 0 = ALLZ mode enabled (Note 3)
GPIO58 Rising Edge of PWROK. GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC. CFG12 ALLZ 1 = Disabled (default)
LAD[3:0]#/FHW[3:0]# PULL-UP 20K
Integrated TPM Enable, Sample low: the Integrated TPM will be disabled. 0 = XOR mode enabled (Note 3)
Rising Edge of CLPWROK Sample high: the MCH TPM enable strap is sampled LAN_RXD[2:0] PULL-UP 20K CFG13 XOR 1 = Disabled (default)
3 SPI_MOSI low and the TPM Disable bit is clear, the
LDRQ[0] PULL-UP 20K CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled 3
Integrated TPM will be enable. 1 = Dynamic ODT Enabled (Default)
LDRQ[1]/GPIO23 PULL-UP 20K
DMI Termination Voltage, The signal is required to be low for desktop 0 = Normal operation(Default):
Rising Edge of PWROK. applications and required to be high for PME# PULL-UP 20K CFG19 DMI Lane Reversal Lane Numbered in Order
GPIO49 mobile applications.
PWRBTN# PULL-UP 20K 1 = Reverse Lanes
DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3)
SATALED# PULL-UP 15K DMI x2 mode[MCH -> ICH]:(3->0,2->1)
PCI Express Lane Signal has weak internal pull-up. Sets bit 27
SATALED# Reversal. Rising Edge of MPC.LR(Device 28:Function 0:Offset D8) SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K
of PWROK. Digital Display Port 0 = Only Digital Display Port
SPI_MOSI PULL-DOWN 20K (SDVO/DP/iHDMI) or PCIE is operational (Default)
SPKR No Reboot. If sampled high, the system is strapped to the CFG20 Concurrent with PCIe 1 =Digital display Port and PCIe are
Rising Edge of PWROK. "No Reboot" mode(ICH9 will disable the TCO Timer SPI_MISO PULL-UP 20K operting simulataneously via the PEG port
system reboot feature). The status is readable
via the NO REBOOT bit. SPKR PULL-DOWN 20K 0 =No SDVO Card Present (Default)
SDVO_CTRLDATA SDVO Present
TACH_[3:0] PULL-UP 20K 1 = SDVO Card Present
TP3 XOR Chain Entrance. This signal should not be pull low unless using
Rising Edge of PWROK. XOR Chain testing. It has a weak internal pull up. TP[3] PULL-UP 20K 0 = LFP Disabled (Default)
Local Flat Panel
USB[11:0][P,N] PULL-DOWN 15K L_DDC_DATA (LFP) Present 1= LFP Card Present; PCIE disabled
GPIO33/ Flash Descriptor Sampled low:the Flash Descriptor Security will be
HDA_DOCK Security Override Strap overridden. If high,the security measures will be
_EN# Rising Edge of PWROK in effect.This should only be enabled in manufacturing NOTE:
environments using an external pull-up resister. 1. All strap signals are sampled with respect to the leading edge of
the (G)MCH Power OK (PWROK) signal.
2 2. iTPM can be disabled by a 'Soft-Strap' option in the
Flash-decriptor section of the Firmware. This 'Soft-Strap' is
2
activated only after enabling iTPM via CFG6.
Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.
SMBus 3. Only one of the CFG10/CFG12/CFG13 straps can be enabled at any time.
SMBC_G792 Thermal
USB Table MXM
USB KBC
Pair Device BAT_SCL
BATTERY
0 USB1
page 31
PCI Routing 1 USB4
IDSEL INT REQ GNT 2 USB2
3 DOCK USB LAN MiniCard
RTS5158 AD25 G:CARDBUS 0 0 WLAN
4 USB3
5 Bluetooth
SMB_CLK
1 PCIE Routing 6 FP
ICH9M
NEW Card MiniCard 970
1
LANE1 LAN BCM5764MKMLG 7 MINIC1 Roboson
LANE2 MiniCard WLAN 8 WEBCAM Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
LANE3 MiniCard Roboson 9 NEW1 Taipei Hsien 221, Taiwan, R.O.C.
LANE4 NewCard 10 MINIC2 Title
SMBC_ICH CK505
11 NC Reference
Size Document Number Rev
DDR A3
Homa -1
Date: Thursday, April 03, 2008 Sheet 2 of 57
A B C D E
1D05V_S0
-1 1 R204 2 3D3V_S0
3D3V_S0 Do Not Stuff
1 R242 2 3D3V_48MPWR_S0 3D3V_CLKPLL_S0 2 R213 1 3D3V_S0
Do Not Stuff Do Not Stuff
Do Not Stuff
1
1
1
1
1
1
1
1
1
1
Do Not Stuff
Do Not Stuff
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
C256 C255 EC58 C221 C253 C239 C252 C250 C248 DY C225
SC1U16V3ZY-GP
DY 3D3V_CLKGEN_S0 1 R202 2
SC4D7U10V5ZY-3GP Do Not Stuff
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
SCD1U16V2ZY-2GP
DY C214 C242 C251 C223 C235 C217
SC4D7U10V5ZY-3GP
2
2
2
2
2
2
4 4
3D3V_48MPWR_S0
3D3V_S0 3D3V_CLKGEN_S0 3D3V_CLKPLL_S0
RN91
5 4 PCLKCLK2
4,7 CPU_SEL2 6 3 CPU_SEL2_R
PCLKCLK4 U15
16
46
62
◦ Jabse Service Manual Search 2026 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo