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5 4 3 2 1
LLW-1/LGG-1 Schematics
D D
Sandy Bridge
Cougar Point
C 2011-01-18 C
REV : -1
DY:None Installed
UMA:UMA platform installed only
B
PX:Discrete(both Robson and Whistler) SKU installed B
RBS:Robson SKU installed only
WTL:Whistler SKU installed only
SAMSUNG:Use SAMSUNG VRAM
Hynix:Use Hynix VRAM
VRAM_1G:Use 1G VRAM
VRAM_2G:Use 2G VRAM
A A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
Cover Page
Size Document Number Rev
A3
LLW-1 / LGG-1 -1
Date: Tuesday, January 18, 2011 Sheet 1 of 94
5 4 3 2 1
PCB Layer Stackup
##OnMainBoard
LLW-1 / LGG-1 Block Diagram L1: TOP
L2: GND
L3: Signal
L5: VCC
L6: Signal
L7: GND
L4: Signal L8: BOTTOM
Battery Charger/Selector
BQ24745 40
VRAM XDP Project Code: 91.4MH01.001
INPUTS OUTPUTS
2GB/1GB88~91 Conn. PCB(Raw Card):10282
11 DCBATOUT BT+
System DC/DC
DDR3
BD95280 41
ThermalSensor PWR_3D3V_DCBATOUT 3D3V_S5
800MHz Channel A UNBUFFERED PWR_5V_DCBATOUT 5V_S5
EMC2103 DDR3 1333 DDR3 SODIMM
28 CPU DC/DC
SM Bus Intel CPU 14 NCP6131 42~44
RFID
AMD GPU Sandy Bridge 204-PIN DDR3 SODIMM
DCBATOUT VCC_CORE
I2C/SM Bus Switch DCBATOUT_VCC_GFXCORE
VCC_GFXCORE
PEG x16
80 Whistler-LP 1G/2G DDR3 1333MHz Channel B 1D05V_VTT
DDR3 1333
UNBUFFERED
Seymour-XT 1G TPS51218 45
DDR3 SODIMM
4~10 PWR_1D05V_DCBATOUT 1D05V_VTT
83~87
15
1D5V_S3
DMI x4 FDI USB 2.0 CH11
TPS51218 46
Mini PCI-E PWR_1D5V_DCBATOUT 1D5V_S3
14" HD PCI Express 4
WLAN Card
65 0D75V
1366*768 LVDS SATA CONN SATA Port 0
49 56 Intel RT9026 46
DDR_VREF_S3
CONN
VGA Port ODD CONN SATA Port 4
PCH PCI Express 2 PCI Express 2
LOM 1D5V_S3
0D75V_S0
VGA connector RJ45
56 RTL8111E
50 USB 2.0 (14 ports) 1D8V_S0
82
SATA
RT8015 47
SIM Mini PCI-E AC97 2.3/Azalia Interface
Media Card Reader 3D3V_S5 1D8V_S0
Slot WWAN Card PCI Express 3
66 66 USB 2.0 CH4 R5U220 VCCSA
Serial ATA 150MB/s 32
RT8208B 48
ACPI 2.0
AUDIO HD AUDIO CODEC PWR_VCCSA_DCBATOUT 0D85V_S0
Azalia bus LPC I/F USB 2.0 CH13 USB 2.0 CH13
COMBO Jack CX20671 29
PCI Rev 2.3 NEW CARD
CONN
58 GFX CORE
PCI Express PCI Express 8 PCI Express 8 RT8208B 92
eSATA Combo CN SATA Port5 INT. RTC
PWR_DCBATOUT_VGA_COREVGA_CORE
USB 2.0 CH10 USB 2.0 CH10 USB 2.0 PORT4
eSATA 82 1V_VGA
CH8
USB 2.0 PORT3 57 RT9025 93
17~25 LPC Bus / 33MHz
1D5V_S3 1V_VGA_S0
USB 2.0 PORT2 CH1 USB 2.0 1D8V_VGA
61
Display Port
RT9025 93
KBC LPC Debug
Nuvoton NPCE795 Board Conn 3D3V_S5 1D8V_VGA_S0
FingerPrint CH2 27 71
USB 2.0
USB 2.0 PORT1 CH9 69
61
HDMI
Bluetooth connector 51 Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
CH3 Taipei Hsien 221, Taiwan, R.O.C.
63 Title
Camera CH12 G-Sensor SPI FLASH Int.KB/Track point
49 Block Diagram
Touch Pad Size Document Number Rev
79 60 69 A3
LLW-1 / LGG-1 -1
Date: Tuesday, January 18, 2011 Sheet 2 of 94
A B C D E
PCH Strapping Huron River Schematic Checklist Rev.0_7 Processor Strapping Huron River Schematic Checklist Rev.0_7
Name Schematics Notes Pin Name Strap Description Configuration (Default value for each bit is Default
SPKR Reboot option at power-up 1 unless specified otherwise) Value
Default Mode: Internal weak Pull-down.
No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k CFG[2] PCI-Express Static 1: Normal Operation.
- 10-k weak pull-up resistor. Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1
Lane Reversal 0:
INIT3_3V# Weak internal pull-up. Leave as "No Connect".
Disabled - No Physical Display Port attached to
GNT3#/GPIO55 GNT[3:0]# functionality is not available on Mobile. CFG[4] 1: Embedded DisplayPort.
4 GNT2#/GPIO53 Mobile: Used as GPIO only
Enabled - An external Display Port device is
0 4
GNT1#/GPIO51 Pull-up resistors are not required on these signals. 0: connectd to the EMBEDDED display Port
If pull-ups are used, they should be tied to the Vcc3_3power rail.
CFG[6:5] PCI-Express 11 : x16 - Device 1 functions 1 and 2 disabled
Enable Danbury: Connect to Vcc3_3 with 8.2-k? weak pull-up resistor. Port Bifurcation 10 : x8, x8 - Device 1 function 1 enabled ;
SPI_MOSI function 2 disabled
Straps 11
Left floating, no pull-down required.
Disable Danbury: 01 : Reserved - (Device 1 function 1 disabled ;
function 2 enabled)
00 : x8, x4, x4 - Device 1 functions 1 and 2
Enable Danbury: Connect to +NVRAM_VCCQ with 8.2-kohm enabled
weak pull-up resistor [CRB has it pulled up
NV_ALE with 1-kohm no-stuff resistor] CFG[7] PEG DEFER TRAINING 1: PEG Train immediately following xxRESETB de assertion
1
Leave floating (internal pull-down) 0: PEG Wait for BIOS for training
Disable Danbury:
NC_CLE DMI termination voltage. Weak internal pull-up. Do not pull low.
Low (0) - Flash Descriptor Security will be overridden. Also,
when this signals is sampled on the rising edge of PWROK
then it will also disable Intel ME and its features. Voltage Rails
HAD_DOCK_EN# High (1) - Security measure defined in the Flash Descriptor will be enabled. POWER PLANE VOLTAGE DESCRIPTION
Platform design should provide appropriate pull-up or pull-down depending on ACTIVE IN
/GPIO[33]
3 the desired settings. If a jumper option is used to tie this signal to GND as 5V_S0
3D3V_S0
5V
3.3V 3
required by the functional strap, the signal should be pulled low through a weak 1D8V_S0 1.8V
pull-down in order to avoid asserting HDA_DOCK_EN# inadvertently. 1D5V_S0 1.5V
1D05V_VTT 1.05V
Note: CRB recommends 1-kohm pull-down for FD Override. There is an internal 0D85V_S0 0.95 - 0.85V
pull-up of 20 kohm for DA_DOCK_EN# which is only enabled at boot/reset for 0D75V_S0 0.75V
strapping functions. VCC_CORE 0.35V to 1.5V
VCC_GFXCORE 0.4 to 1.25V S0
1D8V_VGA_S0 1.8V
3D3V_VGA_S0 3.3V CPU Core Rail
HDA_SDO Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#. 1V_VGA_S0 1V Graphics Core Rail
HDA_SYNC Weak internal pull-down. Do not pull high. Sampled at rising edge of RSMRST#.
Low (1) - Intel ME Crypto Transport Layer Security (TLS) cipher suite with no 5V_USBX_S3 5V
GPIO15 1D5V_S3 1.5V S3
confidentiality High (1) - Intel ME Crypto Transport Layer Security (TLS) cipher DDR_VREF_S3 0.75V
suite with confidentiality
Note : This is an un-muxed signal.
BT+ 6V-14.1V AC Brick Mode only
This signal has a weak internal pull-down of 20 kohm which is enabled when PWROK is low. DCBATOUT 6V-14.1V
Sampled at rising edge of RSMRST#. 5V_S5 5V All S states
CRB has a 1-kohm pull-up on this signal to +3.3VA rail. 5V_AUX_S5 5V
3D3V_S5 3.3V
3D3V_AUX_S5 3.3V
GPIO8 on PCH is the Integrated Clock Enable strap and is required to be pulled-down
GPIO8 using a 1k +/- 5% resistor. When this signal is sampled high at the rising edge of 3D3V_LAN_S5 3.3V WOL_EN Legacy WOL
RSMRST#, Integrated Clocking is enabled, When sampled low, Buffer Through Mode is
enabled.
2 Default = Do not connect (floating) 3D3V_AUX_KBC 3.3V DSW, Sx ON for supporting Deep Sleep states 2
High(1) = Enables the internal VccVRM to have a clean supply for
GPIO27 analog rails. No need to use on-board filter circuit.
Low (0) = Disables the VccVRM. Need to use on-board filter Powered by Li Coin Cell in G3
circuits for analog rails. 3D3V_AUX_S5 3.3V G3, Sx and +V3ALW in Sx
USB Table
Pair Device
SMBus ADDRESSES
PCIE Routing 0 X
1 USB2 I 2 C / SMBus Addresses
HURON RIVER ORB
2 FINGERPRINT Device Ref Des Address Hex Bus
LANE1 RESERVED
3 BLUETOOTH
EC SMBus 1
LANE2 LAN SATA Table 4 Mini Card2 (WWAN) Battery KBC_SDA1/KBC_SCL1
Capacity Board KBC_SDA1/KBC_SCL1
LANE3 CARD READER 5 X EC SMBus 2
SATA PCH KBC_SDA2/KBC_SCL2
6 X MXM KBC_SDA2/KBC_SCL2
LANE4 MiniCard WLAN Pair Device LCD KBC_SDA2/KBC_SCL2
7 X
1 Thermal Sensor
KBC_SDA2/KBC_SCL2
1
LANE5 RESERVED 0 HDD 8 ESATA1
1 mSATA 9 USB1 PCH SMBus Wistron Corporation
CK505 Clock Generator 21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih,
LANE6 RESERVED 2 N/A 10 USB Ext. port 4 SO-DIMMA (SPD) PCH_SMBDATA/PCH_SMBCLK Taipei Hsien 221, Taiwan, R.O.C.
SO-DIMMB (SPD) PCH_SMBDATA/PCH_SMBCLK
Digital Pot PCH_SMBDATA/PCH_SMBCLK Title
LANE7 RESERVED 3 N/A 11 Mini Card1 (WLAN)
PCH_SMBDATA/PCH_SMBCLK
4 ODD 12 CAMERA Table of Content
Size Document Number Rev
LANE8 NEW CARD 5 ESATA 13 New Card A3
-1
LLW-1 / LGG-1
Date: Tuesday, January 18, 2011 Sheet 3 of 94
5 4 3 2 1
SSID = CPU
Signal Routing Guideline:
PEG_ICOMPO keep W/S=12/15 mils and routing length less than 500 mils.
PEG_ICOMPI & PEG_RCOMPO keep W/S=4/15 mils and routing length less than 500 mils.
1D05V_VTT
CPU1A 1 OF 9
J22 PEG_IRCOMP_R R401 1 2 24D9R2F-L-GP
PEG_ICOMPI
19 DMI_TXN[3..0] SANDY PEG_ICOMPO J21
Note: DMI_TXN0 B27 H22
DMI_RX#0 PEG_RCOMPO
D Intel DMI supports both Lane DMI_TXN1
DMI_TXN2
B25
A25
DMI_RX#1 PEG_RXN[0..15]
D
Reversal and polarity inversion DMI_RX#2 PEG_RXN[0..15] 83
DMI_TXN3 B24 K33 PEG_RXN15
but only at PCH side. This is DMI_RX#3 PEG_RX#0 PEG_RXN14
19 DMI_TXP[3..0] PEG_RX#1 M35
enabled via a soft strap. DMI_TXP0 B28 L34 PEG_RXN13
DMI_TXP1 DMI_RX0 PEG_RX#2 PEG_RXN12
B26 DMI_RX1 PEG_RX#3 J35
DMI
DMI_TXP2 A24 J32 PEG_RXN11
DMI_TXP3 DMI_RX2 PEG_RX#4 PEG_RXN10
B23 DMI_RX3 PEG_RX#5 H34
H31 PEG_RXN9
19 DMI_RXN[3..0] DMI_RXN0 PEG_RX#6 PEG_RXN8
G21 DMI_TX#0 PEG_RX#7 G33
DMI_RXN1 E22 G30 PEG_RXN7
DMI_RXN2 DMI_TX#1 PEG_RX#8 PEG_RXN6
F21 DMI_TX#2 PEG_RX#9 F35
DMI_RXN3 D21 E34 PEG_RXN5
DMI_TX#3 PEG_RX#10 PEG_RXN4
19 DMI_RXP[3..0] PEG_RX#11 E32
DMI_RXP0 G22 D33 PEG_RXN3
DMI_RXP1 DMI_TX0 PEG_RX#12 PEG_RXN2
D22 DMI_TX1 PEG_RX#13 D31
PCI EXPRESS* - GRAPHICS
DMI_RXP2 F20 B33 PEG_RXN1
DMI_RXP3 DMI_TX2 PEG_RX#14 PEG_RXN0
C21 DMI_TX3 PEG_RX#15 C32
PEG_RXP[0..15]
PEG_RXP[0..15] 83
J33 PEG_RXP15
PEG_RX0 PEG_RXP14
PEG_RX1 L35
K34 PEG_RXP13
19 FDI_TXN[7:0] FDI_TXN0 PEG_RX2 PEG_RXP12
A21 FDI0_TX#0 PEG_RX3 H35
FDI_TXN1 H19 H32 PEG_RXP11
FDI_TXN2 FDI0_TX#1 PEG_RX4 PEG_RXP10
Note: E19 FDI0_TX#2 PEG_RX5 G34
FDI_TXN3 F18 G31 PEG_RXP9
Intel(R) FDI
Intel FDI supports both Lane FDI0_TX#3 PEG_RX6
FDI_TXN4 B21 F33 PEG_RXP8
Reversal and polarity inversion FDI_TXN5 C20
FDI1_TX#0 PEG_RX7
F30 PEG_RXP7
but only at PCH side. This is FDI_TXN6 FDI1_TX#1 PEG_RX8 PEG_RXP6
D18 FDI1_TX#2 PEG_RX9 E35
C enabled via a soft strap. FDI_TXN7 E17 FDI1_TX#3 PEG_RX10 E33
F32
PEG_RXP5
PEG_RXP4 NOTE.
C
PEG_RX11 PEG_RXP3
19 FDI_TXP[7:0] PEG_RX12 D34 If PEG is not implemented, the RX&TX pairs can be left as No Connect
FDI_TXP0 A22 E31 PEG_RXP2
FDI_TXP1 FDI0_TX0 PEG_RX13 PEG_RXP1
G19 FDI0_TX1 PEG_RX14 C33
FDI_TXP2 E20 B32 PEG_RXP0 PEG Static Lane Reversal
FDI_TXP3 FDI0_TX2 PEG_RX15 PEG_TXN[0..15] 83
G18 FDI0_TX3
FDI_TXP4 B20 M29 PEG_C_TXN15 C401 1 2 PX SCD1U6D3V1KX-GP PEG_TXN15
FDI_TXP5 FDI1_TX0 PEG_TX#0 PEG_C_TXN14 C402 SCD1U6D3V1KX-GP PEG_TXN14
C19 FDI1_TX1 PEG_TX#1 M32 1 2 PX
FDI_TXP6 D19 M31 PEG_C_TXN13 C403 1 2 PX SCD1U6D3V1KX-GP PEG_TXN13
FDI_TXP7 FDI1_TX2 PEG_TX#2 PEG_C_TXN12 C404 SCD1U6D3V1KX-GP PEG_TXN12
F17 FDI1_TX3 PEG_TX#3 L32 1 2 PX
L29 PEG_C_TXN11 C405 1 2 PX SCD1U6D3V1KX-GP PEG_TXN11
PEG_TX#4 PEG_C_TXN10 C406 SCD1U6D3V1KX-GP PEG_TXN10
19 FDI_FSYNC0 J18 FDI0_FSYNC PEG_TX#5 K31 1 2 PX
Note: J17 K28 PEG_C_TXN9 C407 1 2 PX SCD1U6D3V1KX-GP PEG_TXN9
19 FDI_FSYNC1 FDI1_FSYNC PEG_TX#6
Lane reversal does not apply to J30 PEG_C_TXN8 C408 1 2 PX SCD1U6D3V1KX-GP PEG_TXN8
PEG_TX#7 PEG_C_TXN7 C409 SCD1U6D3V1KX-GP PEG_TXN7
FDI sideband signals. 19 FDI_INT H20 FDI_INT PEG_TX#8 J28 1 2 PX
H29 PEG_C_TXN6 C410 1 2 PX SCD1U6D3V1KX-GP PEG_TXN6
PEG_TX#9 PEG_C_TXN5 C411 SCD1U6D3V1KX-GP PEG_TXN5
19 FDI_LSYNC0 J19 FDI0_LSYNC PEG_TX#10 G27 1 2 PX
H17 E29 PEG_C_TXN4 C412 1 2 PX SCD1U6D3V1KX-GP PEG_TXN4
19 FDI_LSYNC1 FDI1_LSYNC PEG_TX#11
F27 PEG_C_TXN3 C413 1 2 PX SCD1U6D3V1KX-GP PEG_TXN3
1D05V_VTT PEG_TX#12 PEG_C_TXN2 C414 SCD1U6D3V1KX-GP PEG_TXN2
PEG_TX#13 D28 1 2 PX
F26 PEG_C_TXN1 C415 1 2 PX SCD1U6D3V1KX-GP PEG_TXN1
PEG_TX#14 PEG_C_TXN0 C416 SCD1U6D3V1KX-GP PEG_TXN0
PEG_TX#15 E25 1 2 PX
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