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SERIAL PORT CONTROLLER
MANUAL
CGC 7900 SERIES
COLOR GRAPHICS COMPUTERS
CHROMATICS
CGC 7900 Series
Serial Port Controller
Application Guide
CHROMATICS
CGC 7900 SERIES COLOR GRAPHICS COMPUTER SYSTEM
SERIAL PORT CONTROLLER (SPC)
APPLICATION GUIDE
Copyright (c) 1982 by Chromatics, Inc.
2558 Mountain Industrial Boulevard
Tucker, Georgia 30084
Phone (404) 493-7000
TWX 810-766-8099
May, 1982
Serial Port Controller Application Guide Page 1
IRTRoDUcrmH
This Application Guide describes the Serial Port Controller, or SPC, an
optional card in Chromatics', CGC 7900 series. The SPC is designed to handle
low-level data communications chores in the 7900 system, for up to 4 RS-232
ports.
By relieving the main CPU of the burden of handshaking and buffering, the
SPC can greatly enhance system throughput. The SPC contains its own Z80
processor, and firmware which runs the normal "read character, write character"
operations. This Application Guide is intended for the user who wants to
customize SPC firmware for special purposes. We will discuss the SPC
architecture, and provide programming examples.
This document is written tor the experienced prograuaer. The SPC firmware
is written in Z80 assembly language, and you will need access to a Z80 assembler
and development system, or a compiler capable of generating Z80 code. For
high-speed applicatiOns, running one or more ports at high baud rates, you will
probably' have to write the majority of the firmware directly in assembly language
for efficiency. Current SPC firmware was developed on Chromatics' CG series
color graphic computer systems.
We will begin by describing the SPC, its architecture, and how it operates
in a standard CGC 7900 system. From there, we will proceed to the advanced
features of the hardware, including some which are not normally used (but are
installed). These features include the ability to run one or more ports with
external clocks; daisy-chaining up to four SPC boards in a system; and
interrupt-driven I/O.
Other CGC 7900 documentation available from Chromatics includes the CGC 7900
User's Manual, OEM Manual, and Disk Operating System Manual. Additional SPC
documentation includes the circuit descriptions, test procedures, schematiCS, and
source listing for the firmware. Some of this documentation is considered
proprietary, and you may be required to file a non-disclosure agreement.
Page 2 Chromatics CGC 7900 Series
Serial Port Controller Application Guide Page 3
ARCHITECTURE
The SPC consists of a Z80 processor running at 2.5 MHz, two 2532-type EPROMs
for onboard firmware (up to 8K bytes), 4K bytes of onboard RAM, and 1K bytes of
two-port RAM. The four serial ports are each handled by a 2661 Enhanced
Programmable Communications Interface (a friendly USART). The remainder of the
circuitry is "glue" logic which holds the system together, and provides
interrupts, interprocessor Signalling, and i/o decoding.
The SPC is, in fact, a complete Z80 computer system. It only requires a few
signals from the 1900 bus in order to function. This means that the SPC can
continue to run during times when the main 68000 system processor is unable to
operate (during DMA transfers, for example). Within the 4K of onboard memory,
each port has two buffers (transmit and receive), each of which is 256 bytes
long. A substantial amount of data can be buffered in this onboard RAM before
68000 intervention is required.
The memory map on the following page details the SPC memory allocation.
Onboard EPROM occupies 0000 through 1FFF hex. Two-port RAM is from 2000 to 23FF.
All i/o is memory-mapped, and resides from 3000 to 301F. This includes the 2661
chips and the Flags (used for signalling between processors). Onboard RAM is
located at 1000 through 1FFF. Most of onboard RAM is available for buffer area,
although a small amount must be used for the Z80 stack and temporary data storage
areas.
From the 68000 point of view, the SPC occupies 2K of address space, from
FFOOOO to FF01FF. All odd-numbered bytes in this range are mapped into the
two-port RAM. Even bytes are used to access the Flags. Since the SPC is an
8-bit system, all 68000 programs talking to it must use 8-bit (byte) operations
only. Using word or long word instructions will cause unhappy behavior.
The 68000 can only address the two-port RAM and the Flags. It cannot access
other items in the SPC address space directly; that is the Z80's job.
The two-port RAM (known as TRAM) is the method by which the two processors
communica te their needs. The firmware contains a set of commands which can be
passed to the Z80 in TRAM; the Z80 will act on these commands and return results
to the 68000. The command set is described in a later section of this document.
Current SPC firmware occupies only the first of the two EPROM sockets. The
second EPROM is available for user-written firmware at this time. Chromatics
reserves the right to expand SPC functions and utilize the second EPROM at some
future date... swim at your own risk.
Page 4 Chromatics CGC 7900 Series
MEMORY MAP
- Z80 Side -
0000 - OFFF EPROM 10
1000 - 1FFF EPROM 11
2000 - 23FF Two-port RAM
3000 - 301F I/O space: USARTs, flags
7000 - 7FFF Onboard RAM
I/O space is allocated as follows:
3000 Port 0 data
3001 Port 0 status
3002 Port 0 mode
3003 Port 0 command
3004 - 3007 Port 1 (as above)
3008 - 300B Port 2
300C - 300F Port 3
3010 RTC reset
3018 Flag 1 (read examines, write SETs)
3019 Flag 2 (read examines, write CLEARs)
301C Flag 3 (read or write interrupt's 68000)
- 68000 Side -
FFOO01 - FF07FF (odd bytes only) Two-port RAM
FFOOOO Flag 1 (read examines, write CLEAR s)
FFOO02 Flag 2 (write SETs Z80 interrupt)
FFOO04 Flag 4 (write RESETs Z80, read allows
Z80 to run)
FFOO06 Flag 3 (write CLEARs 68000 interrupt)
Serial Port Controller Application Guide Page 5
NOTE: Due to redundant addressing, some items also appear at
addresses other than those listed above. For example, on the
Z80 side, TRAM also appears at 2400-27FF, 2800-2BFF, and
2COO-2FFF. On the .68000 side, TRAM is uniquely addressed,
but the Flags are not. Therefore, programmers should be
careful not to access any addresses other than those listed
above.
Since the SPC is inherently an 8-bit device, all 68000 programs using the
SPC should use ~ instructions only. Using 16-bit or 32-bit instructions will
access the TRAM and the Flags simultaneously, causing strange results. Be
espec:i.aJ.ly careful when accessing the two-port RAM: the program must read a byte,
skip over a byte, and read the next byte from the next odd address. A sample
program fragment might be:
LEA TRAM,AO jAO -> 2-~rt RAM
Loop MOVE.B (AO)+,(A1)+ jCopy one byte from TRAM
ADDQ.L 11,AO ;sk1p odd bytes
DBRA DO,Loop icontinue
NOTE: Any time the Z80 accesses Flag 3, whether during a read OR a
write, it will set an interrupt to the 68000. Be careful
when examining memory in the I/O space, since reading it can
cause unwanted interrupts.
Page 6 Chromatics cac 7900 Series
Serial Port Controller Application Guide Page 7
FIlUIlARE
The SPC firmware operates with the 7900 Terminal Emulator, TERMEM. Version
2 firmware, and later versions, also support the leiris operating system.
Interaction with Idris is more complex than TERMEM, and we will describe TERMEM
first.
It is TERMEM's purpose in life to read characters from logical devices and
write them to other logical devices. A device aSSignment structure allows each
logical device to be "connected" to one or more physical devices. Each of the
ports on the SPC is considered to be one physical device, assignable for input,
output, or both.
When TERMEM is running with the SPC, two basic operations are possible:
write a character to a port, and read a character from a port. TERMEM operates
on a character-at-a-time basiS, so more complex interactions are not required. A
third operation "reconfigures" a port, setting up baud rate, handshaking, and
character format. Each of these is discussed in the "Commands" section of this
document.
When the SPC is powered-up or reset, the Z80 begins executing code from its
onboard EPROM. It initializes the four serial ports with default parameters, and
enters a simple loop which performs these functions:
Service port o.
Service port 1.
Service port 2.
Service port 3.
Check for commands from the 68000, and process
them if necessary.
To service any port, the zao reads the port status from the 2661 chip. If a
character has been received, it is loaded into onboard RAM. If a buffer becomes
full, the proper handshaking protocol is performed. Then the transmitter side of
the port is serviced. If a port shows "transmitter ready," a character is pulled
from onboard RAM and trans.mitted. The ◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo