Service Manuals, User Guides, Schematic Diagrams or docs for : . Various 20050812095225703_7_Schematic_Diagram
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[CONTENTS]
Sheet 1. Cover & Contents
Sheet 2-6. BLOCK / POWER / CLK / PLATFORM INFO / RESET
Sheet 7. Clock Generator
SENS V20 Series
Sheet 8-9. CPU (Pentium-IV)
Sheet 10. Thermal Sensor
3-1 Main Board
Sheet 11-13. 845G
Sheet 14. 845G GLUE LOGIC
DRACO Sheet 15. CH7017
Sheet 16. LCD / CRT
3-1-1 Schematic Diagrams
Sheet 17. SDR MEMORY
CPU : Pentium-IV Sheet 18-20. ICH4
Chip Set : Brookdale-GL / ICH4 Sheet 21. FWH
Sheet 22. MICOM
Sheet 23. MICOM GLUE LOGIC
Model Name : DRACO Sheet 24. POWER LED / KBD / PS2 / TOUCHPAD
PBA Name : MAIN BOARD Sheet 25. AC97 CODEC
Sheet 26. AMP / SPK / MIC / SPDIF
PCB Code : Sheet 27. HDD / CD
Dev. Step : MP Sheet 28. CARDBUS CONTROLLER
Sheet 29. CARDBUS SOCKET
Revision : 1.0 Sheet 30. 1394 Controller & PHY
T.R. Date : Aug, 15, 2002 Sheet 31. SUPER I/O
Sheet 32. PIO & USB
3 Schematic Diagrams and PCB Silkscreen
Sheet 33. Kinnereth & MDC
Sheet 34. MINIPCI
DRAW CHECK APPROVAL Sheet 35. LED / SWITCH
Sheet 36. DC Jack & B/D to B/D & bypass
Sheet 37. CHARGING CIRCUIT
Sheet 38. CPU DC/DC
W.S. Jung H.J. KIM Kevin, Lee
Owner : Signature : X
3-1
3-2
DRACO Block Diagram
Charging
LCD Circuit
PG 37
2 FAN System CLK GEN
PG 20 Pentium-IV Smart
CPU DC/DC
14.1 Battery
15 DC/DC Module PG 7
CPU
L2 Cache : 512KB
Thermal 478 PGA PG38 Life Time > 2Hrs
Sensor PG 8,9
PG 16
30Pin Connector
PG 10
PG 17
PSB
400MT/S SDR-SODIMM 1
CH7017 DVO I/F, 1.5V PG 17
TV
3 Schematic Diagrams and PCB Silkscreen
LVDS & TV SDR 3.3V, 133MHz
SDR-SODIMM 0
PG 15 Brookdale-G/GL
CRT 760 BGA
PG 16
PG 11,12,13
ANT ANT
PG 32 Hub Interface MINIPCI
USB0 8Bit, 1.5V, 266MB/S Wireless LAN
PG 34
USB1
USB 2.0 SUPPORT 33MHz, 3.3V PCI
HDD
ICH4
U-ATA 100 Primary IDE 421 BGA LAN
PG 27 Kinnereth(LAN PHY) CARDBUS 1394
PG 18,19,20 AC97
ODD(CD/DVD/RW/COMBO) Secondary IDE MDC Modem
R5C475II TSB43AB22
U-ATA 100
PG 27 PG 33 PG 28 PG 30
3-1-1(a) Main Board Schematic Sheet 2 of 39(CLOCK GENERATOR)
RJ45 RJ11
Audio Power SOCKET
AC97 Link 1 TYPE II
CS4202 FWH PG 29 PG 29
PG 25 3.3V LPC, 33MHz
PG 21
SPDIF
Super I/O SMC/KBC
PC87391 Hitachi H8S Mouse,KBD
H-PHONE 2169
PG 31 PG 22
MIC-IN
Scan Touch
KBD PAD PS/2
Serial Parallel PG 24 PG 24
PG 24
PG 32
SENS V20 Series
Power Diagram
SENS V20 Series
VDC
MICOM_P3V
MICOM
KBC3_SUSPWR QS3257
KBC3_COREON
KBC3_PWRON
P3.3V_AUX P1.5V_AUX P5V
ICH4 ICH-4
LAN
MODEM ICH4
M_PCI FAN
ADM1032 CRT
CARDBUS Cont. CARDBUS Cont.(R5C475II)
MICOM USB
SODIMM PS/2
HDD
M_PCI
ODD AVDD
FDD
MICOM
KBC3_PWRON MDC MODEM
TOUCHPAD AUDIO
LEDs SPK-AMP
MIC-AMP
VCC_VID
3-1-1(b) Main Board Schematic Sheet 3 of 39(POWER DIAGRAM)
PCORE (1.2V)
P3.3V P1.5V P12V
845GL CARDBUS Cont.(R5C485)
Pentium-IV Pentium-IV 845GL
W320 ICH4
ICH-4
VID Pull-Up CARDBUS Cont.(R5C485)
ADM1032 VCH
CH7017
ICH4
FWH
CBT3384
MK1707 ?
LCD
MICOM
CARDBUS Cont.
SUPERI/O
SIO
M_PCI
LEDs
VCH
1394
3-3
3 Schematic Diagrams and PCB Silkscreen
3-4
CLK Diagram
100MHz Differential CLK
PENTIUM-IV
400MHz STB/STB#
100MHz Differential CLK 133MHz
MCLK 0/1 SDR SODIMM 0
66MHz FOR HUB LINK
845-G 133MHZ
48MHz FOR DISPLAY
MCLK 2/3 SDR SODIMM 1
C 66MHz DVO
66MHz HUB LINK
12.288MHz FOR AC97
66MHz FOR HUB LINK 48KHz FOR AC97 SYNC 24.576MHz FOR AC97
L AC97 AUDIO CODEC
33MHz FOR PCI MC97 MODEM CODEC
48MHz FOR USB ICH-4 5 ~ 50MHz
3 Schematic Diagrams and PCB Silkscreen
Kinnereth LAN PHY 25MHz
14.318MHz FOR 8254 TIMER
K 32.768KHz
14.318MHz CH7017
40MHz FOR SVGA LCD
65MHz FOR XGA
G 33MHz FOR LPC
FWH
E 33MHz FOR LPC
MICOM 10MHz
3-1-1(c) Main Board Schematic Sheet 4 of 39(CLK DIARAM)
33MHz FOR LPC
14.318MHz FOR I/O SUPER I/O
N FONT : STROKE => HELVETICA
33MHz FOR PCI HEIGHT : 0.2 => 0.25
CARDBUS Cont.
* => #
ROADMAPPER Height : 0.1 => 0.15
33MHz FOR PCI
1394 Controller 24.576MHz pin_group : change attribute - visibility
NO_STUFF : helvetica bold , 0.25
33MHz FOR PCI
Mini-PCI
14.318MHz
SENS V20 Series
SENS V20 Series
DRACO REFERENCE PLATFORM
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
2
PCI Devices I C / SMB Address
Devices IDSEL# REQ/GNT# Interrupts Devices Address Hex Bus
Cardbus AD19 0 A,B ICH4 Master - SMBUS Master
AGP AD17(internal) - A,B ADM1032 (CPU Thermal Sensor) 0100 110x 4Ch Thermal Sensor
MiniPCI AD23 2 A,B SODIMM0 1010 000x A0h SDR SODIMM0
Kinnereth AD24(internal) - - SODIMM1 1010 000x A2h SDR SODIMM1
USB AD29(internal) - USB2.0 #0 : A CK-Titan (Clock Generator) 1101 001x D2h Clock, Unused Clock Output Disable
USB2.0 #1 : D LVDS & TV Encoder(CH7017) 1110 101x EAh I2C BUS
Hub to PCI AD30(internal) -
LPC bridge/IDE/AC97/SMBUS AD31(internal) - B
CPU Core Voltage Table USB PORT Assign
PORT NUMBER ASSIGNED TO
VID4 VID3 VID2 VID1 VID0 Voltage VID4 VID3 VID2 VID1 VID0 Voltage
0 SYSTEM A
0 1 1 0 0 1.550 V 1 0 1 1 0 1.300 V
0 1 1 0 1 1.525 V 1 0 1 1 1 1.275 V 2 SYSTEM B
0 1 1 1 0 1.500 V 1 1 0 0 0 1.250 V
0 1 1 1 1 1.475 V 1 1 0 0 1 1.225 V
1, 3~5 (RESERVED)
1 0 0 0 0 1.450 V 1 1 0 1 0 1.200 V
1 0 0 0 1 1.425 V 1 1 0 1 1 1.175 V
1 0 0 1 0 1.400 V 1 1 1 0 0 1.150 V
1 0 0 1 1 1.375 V 1 1 1 0 1 1.125 V
1 0 1 0 0 1.350 V 1 1 1 1 0 1.100 V
1 0 1 0 1 1.325 V 1 1 1 1 1 VRM output off
3-1-1(d) Main Board Schematic Sheet 5 of 39(PLATFORM INFORMATION)
REVISION HISTORY
See rev notes in the changes file for more information.
3-5
3 Schematic Diagrams and PCB Silkscreen
3-6
RESET DIAGRAM
CPU1_CPURST#
PCI3_RST#
CPU1_PWRGDCPU
KBC3_PWRGD
3 Schematic Diagrams and PCB Silkscreen
VRM3_PWRGD
PCORE
VID_PWRGD
P5V
3-1-1(e) Main Board Schematic Sheet 6 of 39(CLK GEN)
P3.3V
KBC3_PWRON
CHP3_SLP3#
KBC3_RSMRST#
P3.3V_AUX
KBC3_SUSPWR
KBC3_PWRSW#
SENS V20 Series
SENS V20 Series
Clock Generator
S1 S0 HOST CLK
0 0 66MHz
0 1 100MHz @
1 0 200MHz
1 1 133MHz future use
CPU3_BSEL0
SMB3_CLK
SMB3_DATA
NO_STUFF CLK0_HCLK0#
CLK0_HCLK0 CLK3_ICH66
CLK3_MCH66
CLK0_HCLK1#
CLK0_HCLK1
CLK3_PCLKICH
KBC3_VRPWRGD#
CLK3_PCLKCB
CLK3_PCLK1394
CLK3_PCLKFWH
CLK3_PCLKSIO
CLK3_PCLKMICOM
CLK3_PCLKMIN
NO_STUFF CLK3_DOT48
CLK3_ICH48
CLK3_SIO14
CLK3_ICH14
3-1-1(f) Main Board Schematic Sheet 7 of 39(CLK GEN)
Place near to Receiver
NO_STUFF
KBC3_VRPWRGD#
3-7
3 Schematic Diagrams and PCB Silkscreen
3-8
Northwood Processor
CPU1_A(16:3)
CPU1_ADS# CPU1_D(15:0) CPU1_D(47:32)
CPU1_BNR#
CPU1_ADSTB0# CPU1_BREQ#
CPU1_BPRI#
CPU1_DBI0# CPU1_DBI2#
CPU1_DBSY# CPU1_DSTBN0# CPU1_DSTBN2#
CPU1_DEFER# CPU1_DSTBP0# CPU1_DSTBP2#
CPU1_REQ#(4:0) CPU1_DRDY# CPU1_D(31:16) CPU1_D(63:48)
CPU1_HIT#
CPU1_HITM#
3 Schematic Diagrams and PCB Silkscreen
CPU1_A(31:17)
CPU1_INIT#
CPU1_LOCK#
CPU1_CPURST#
CPU1_RS2#
CPU1_RS1#
CPU1_RS0#
CPU1_TRDY# CPU1_DBI1# CPU1_DBI3#
CPU1_DSTBN1# CPU1_DSTBN3#
CPU1_DSTBP1# CPU1_DSTBP3#
CPU1_ADSTB1#
CHP3_CPUPERF#
CPU1_A20M#
CPU1_IGNNE# Table A ITP I/F Board Signal
CPU1_INTR
3-1-1(g) Main Board Schematic Sheet 8 of 39(Pentium-IV [1/2])
CPU1_NMI
CPU1_SMI# To use ITP Debugginh Mode, Do not install
the resistors on the TCK, TDI, and TMS.
CPU1_STPCLK#
CPU1_INIT# And connect ITP I/F Board
CPU1_SLP# 1 PCORE
2 CPU1_CPURST*
3 CPU1_TCK
4 CPU1_TMS
5 CPU1_TDI
6 CPU1_TDO
7 PVCCT
8 CPU1_TRST*
9 CPU1_PREQ*
NO_STUFF 10 CPU1_PRDY*
SMB3_ALERT# 11 GND
12 CLK2_HCLK1
13 GND
CPU1_PROCHOT#
SENS V20 Series
Northwood Processor
SENS V20 Series
CLK0_HCLK0 CPU3_BSEL0
CLK0_HCLK0#
CPU1_A20M#
CPU1_FERR# ITP I/F Signal
CPU1_IGNNE# PREQ*
PRDY*
BPM1
CPU1_INTR BPM0
CPU1_NMI DBRST*
CPU1_SMI#
CPU1_STPCLK#
CPU3_VID(0:4)
4.7uH at 80mA
10uH at 60mA CPU_GTLREF0
CPU2_THERMDA
CPU2_THERMDC
22~100uF CPU1_THRMTRIP#
ESR<0.3ohm CPU1_PWRGDCPU
ESL<5nH
Tol +/-20% CPU1_PROCHOT#
CPU1_SLP#
Alternative
4.7uH : 2703-001816
44uF : 2402-001045,7343
TEST ONLY
3-1-1(h) Main Board Schematic Sheet 9 of 39(Pentium-IV [2/2])
GTL REFERENCE
CPU_GTLREF0
Keep the Voltage divider within 1.5" of the first GTLREF pin.
Don t allow signal line to use the GTLREF routing as part of their return path.
3-9
3 Schematic Diagrams and PCB Silkscreen
3-10
CPU3_THRMTRIP#
KBC3_COREON
KBC3_PWRON
VRM3_PWRGD
CPU3_THRMTRIP#
CPU3_VID(0:4)
CPU1_THRMTRIP#
3 Schematic Diagrams and PCB Silkscreen
1.2V, Max-300mA
VID POWER
[ 350mA ]
VID_PWRGD
KBC3_PWRON
Refer To Thermal Sensor Layout Guidelines.
3-1-1(i) Main Board Schematic Sheet 10 of 39(THERMAL SENSOR)
CPU Thermal Sensor - Place the Thermal Sensor close to a remote diode.
- Keep traces away from high voltage (+12V bus)
- Keep traces away from fast data buses and CRTs.
- Use recommended trace widths and spacings (10mil)
KBC3_THERM_SMCLK CPU2_THERMDA - Place a ground plane under the traces.
KBC3_THERM_SMDATA
SMB3_ALERT# CPU2_THERMDC - Use guard traces flanking DXP and DXN and connecting to GND
THERM3_OVERT#
ADM1032ARM
SENS V20 Series
BROOKDALE-GL (1/3)
CLK3_DOT48
VGA3_VSYNC
VGA3_HSYNC
VGA_BLUE#
VGA_BLUE CPU3_BSEL0
VGA_GREEN#
SENS V20 Series
VGA_GREEN
VGA_RED#
VGA_RED
VGA3_DDCC
VGA_RED VGA3_DDCD
CPU1_A(31:3) CPU1_D(63:0)
VGA_GREEN
VGA_BLUE
CPU1_REQ#(4:0)
CPU1_ADSTB0#
CPU1_ADSTB1#
CLK0_HCLK1
CLK0_HCLK1#
MCH_HVSWING1
MCH_HVSWING0
CPU1_DSTBP0#
CPU1_DSTBN0#
CPU1_DBI0#
3-1-1(j) Main Board Schematic Sheet 11 of 39(845GL [1/3])
CPU1_DSTBP1#
CPU1_DSTBN1#
CPU1_DBI1#
MCH_HVSWING0 CPU1_DSTBP2#
CPU1_DSTBN2#
CPU1_DBI2#
CPU1_DSTBP3#
CPU1_DSTBN3#
CPU1_DBI3#
FOR SDR SDRAM
CPU1_ADS#
CPU1_TRDY#
CPU1_DRDY#
MCH_HVSWING1 CPU1_DEFER#
CPU1_HITM#
CPU1_HIT#
CPU1_LOCK#
CPU1_BREQ#
CPU1_BNR#
CPU1_BPRI#
CPU1_DBSY#
CPU1_RS0#
CPU1_RS1#
CPU1_RS2#
CPU1_CPURST#
KBC3_PWRGD
Reference Voltage Input for Compensation Logic.
Routing : 12 mil trace, 10 mil space
3-11
3 Schematic Diagrams and PCB Silkscreen
3-12
BROOKDALE-GL (2/3)
MEM3_MAA(0:12) MEM3_MD(63:0)
MEM3_CKE0
MEM3_CKE1
MEM3_CKE2
MEM3_CKE3
CLK3_MCLK0
CLK3_MCLK1
CLK3_MCLK2
3 Schematic Diagrams and PCB Silkscreen
CLK3_MCLK3
MEM3_CSA0#
MEM3_CSA1#
MEM3_CSA2#
MEM3_CSA3#
MEM3_DQMA(0:7)
MEM3_BS0
MEM3_BS1
MEM3_SRASA#
MEM3_SCASA#
MEM3_MWEA#
3-1-1(k) Main Board Schematic Sheet 12 of 39(845GL [2/3])
NO_STUFF
NO_STUFF
As close as possible
SDRAM only
within 0.5" from GMCH
at least 10mA
CLK3_MCLK0
CLK3_MCLK1
SENS V20 Series
SENS V20 Series
BROOKDALE-GL (3/3)
HUB1_STBF DVOB1_CLK
HUB1_STBS DVOB1_CLK#
CLK3_MCH66 DVOB1_HSYNC
DVOB1_VSYNC
HUB1_HL(0:10) DVOB1_FLDSTL
DVOB1_BLANK#
DVOB1_D(0:11)
HI_VREF_GMCH
HI_VSWING_GMCH
PCI3_RST# DVOC1_CLKOUT
DVOC1_CLKOUT#
DVOC1_HSYNC
DVOC1_VSYNC
DVOC1_FLDSTL
ADD_DETECT#
DVO device down scenario DVOC1_BLANK#
DVOC1_D(0:11)
3-1-1(l) Main Board Schematic Sheet 13 of 39(845GL [3/3])
TV1_CLKOUT
DVO device down scenario
MI2C1_CLK
MI2C1_DATA
3-13
3 Schematic Diagrams and PCB Silkscreen
3-14
Between GMCH and ICH
GMCH bypass for 845G
0.25" LESS
0.7V, 2% HI_VSWING_GMCH
HI_VSWING_ICH 0.1uF X 15
22uF X 2
150uF X 3
3 Schematic Diagrams and PCB Silkscreen
0.35V, 2% HI_VREF_GMCH
HI_VREF_ICH
0.1uF X 10
10uF X 3
3-1-1(m) Main Board Schematic Sheet 14 of 39(845GL Bypass)
0.1uF X 6
10uF X 2
100uF X 1
SENS V20 Series
VDDV
SENS V20 Series
VDDV VREF1
(VDDV/2)
VDDV
VREF1
NO_STUFF
TV1_CLKOUT VGA5_DDCC
VGA3_DDCC VGA5_DDCD
VGA3_DDCD
MI2C1_CLK
MI2C1_DATA VCH3_Y
VCH3_C
PCI3_RST#
DVOB1_CLK
DVOB1_CLK#
DVOB1_HSYNC
DVOB1_VSYNC
DVOB1_BLANK#
DVOB1_FLDSTL
DVOB1_D(0:11)
NO_STUFF
VGA3_VSYNC
VGA5_VSYNC
VGA3_HSYNC
VGA5_HSYNC NO_STUFF
VCH3_LCDVDDON
VCH3_BKLTON
LVDS1_ACLK+
LVDS1_ACLK-
LVDS1_A0+
DVOC1_CLKOUT LVDS1_A0-
DVOC1_CLKOUT# LVDS1_A1+
DVOC1_HSYNC LVDS1_A1-
3-1-1(n) Main Board Schematic Sheet 15 of 39(VCH)
DVOC1_VSYNC LVDS1_A2+
DVOC1_BLANK# LVDS1_A2-
DVOC1_FLDSTL
DVOC1_D(0:11)
VGA3_DDCC
VGA3_DDCD
VGA3_VSYNC
VGA3_HSYNC VGA5_DDCC
VGA5_DDCD
VGA5_VSYNC
VGA5_HSYNC
PIN35(LGND6)
CHP3_PAL_NTSC#
3-15
3 Schematic Diagrams and PCB Silkscreen
3-16
Main To LCD Connector
NO_STUFF
LCD3_BKLTON IVT_VDC
LCD5_BRIT
VCH3_BKLTON
LCD3_BKLTON
KBC3_BKLTON LVDS1_ACLK+
LVDS1_ACLK-
LVDS1_A2+
LVDS1_A2-
LVDS1_A1+
LVDS1_A1-
LCD_VDD3V LVDS1_A0+
LVDS1_A0-
KBC3_BRIT
3 Schematic Diagrams and PCB Silkscreen
LCD5_BRIT
17-A
LCD_VDD3V
CRT
VCH3_LCDVDDON
VGA_RED
3-1-1(o) Main Board Schematic Sheet 16 of 39(LCD & CRT)
VGA_GREEN
VGA_BLUE
VGA5_DDCD
VGA5_DDCC
VGA5_HSYNC
VGA5_VSYNC
Close to VGA as possible
VGA_RED#
NO_STUFF
VGA_GREEN#
VGA_BLUE#
SENS V20 Series
SLOT 0 REVERSE TYPE SODIMM (Only PC-133) SLOT 1
MEM3_MD(0:63) MEM3_MD(0:63)
SENS V20 Series
Add one 10nF Cap X7R per 5 signals that switch plane references.
1G Max
MEM3_DQMA(7) MEM3_DQMA(3) MEM3_DQMA(7) MEM3_DQMA(3)
MEM3_DQMA(6) MEM3_DQMA(2) MEM3_DQMA(6) MEM3_DQMA(2)
MEM3_MAA(0) MEM3_MAA(3) MEM3_MAA(0) MEM3_MAA(3)
MEM3_MAA(1) MEM3_MAA(4) MEM3_MAA(1) MEM3_MAA(4)
MEM3_MAA(2) MEM3_MAA(5) MEM3_MAA(2) MEM3_MAA(5)
CLK3_MCLK0 MEM3_CKE0 CLK3_MCLK2 MEM3_CKE2
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