Service Manuals, User Guides, Schematic Diagrams or docs for : . Various 20070327164051562_12_Schematic_Diagram
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4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Table of Contents D
Sheet 1. COVER
HAINAN C Sheet 2 - 7. DIAGRAM (Block/Power) & ANNOTATIONS
Sheet 8. CLOCK GENERATOR
Sheet 9 - 11. YONAH667 / MEROM CPU(TBD)
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Sheet 12. THERMAL SENSOR / FAN CONTROL
Sheet 13 - 17. CALISTOGA-GMCH
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Sheet 18. DDR II SODIMM
CPU :Intel Yonah/Merom Sheet 19. DDR TERMINATION
Sheet 20 - 23. ICH7-M
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Chip Set :Intel Calistoga & ICH7-M Sheet 24. FWH
Sheet 25. LVDS CONNECTOR
Remarks : Mobility Platform
s n
C
Sheet 26. CRT CONNECTOR
Sheet 27 -28. R5C843 CARDBUS CONTROLLER
Sheet 29. EXPRESS & PCMCIA CONNECTOR
m e
Sheet 30. WIBRO & SIM CARD
Sheet 31. MINI PCI EXPRESS & DMB & IR
Model Name : HAINAN C Sheet 32 - 34. AUDIO
a id
Sheet 35. HDD ODD CONNECTOR
PBA Name : MAIN Sheet 36. MICOM
S f
Sheet 37. LAN CONTROLLER
PCB Code : BA41-00694A GCE Sheet 38. RJ45, RJ11, LED LOGIC
BA41-00695A TPT Sheet 39. SUB BOARD CONNECTOR
Sheet 40. CHARGER
Dev. Step : MP Sheet 41. P3.3V_LAN & P5V_AUX
n
Sheet 42. P1.5V & VCCP
Revision : 1.0 Sheet 43. DDR2 POWER B
o
Sheet 44. CPU VRM (SEMTECH)
T.R. Date : 2006.07.17 Sheet 45. MICOM RESET & SWITCHED POWER
Sheet 46. DISCHARGING LOGIC
C
Sheet 47. BIOS DEBUG
Sheet 48 - 49. SUB BOARD
DRAW CHECK APPROVAL
BW YOO SS BAIK KK BIN
A
SAMSUNG
Owner : SEC Mobile R & D Signature : X ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
FAN CPU
D
Mobile Processor VRM
D
PG 12
IMVP-6
Yonah - 2M Graphic
CPU Charging Core
LCD Thermal (667MHz) PG 51
Circuit
30P Sensor
PG 12 L2 Cache : 2 MB PG 47 PG 53
PG 32 PG 9,10,11 478pin
DDR II
CRT
LVDS PSB Thermistor
667 MT/S PG 16 DDR II Switche PWR
CRT VRM
PG 46
Ext. PEG
g l
External Graphics PG 52
PEG x16 DDR II PG 18 PG 50
Channel A (Standard)
nVidia NV43M
PG 25 ~ 28
SODIMM 0
GMCH-M Dual channel DDR II 667/533
n a
PG 18
DDR II
Calistoga-GM Channel B (Reverse)
SODIMM 1
Video Memory
u ti
1466 FCBGA
64MB : K4D26323QG
128MB : K4D55323QF
PG 34
PG 30 ~ 31 Internal Graphics
s n
LVDS PG 13 ~ 17 SD/xD/MS
C PG 34 C
CRT/TV CARDBUS
Direct Media Interface CardBus
x4/x2, 1.5V R5C843 PG 34
Ext. - Int. Option EEPROM
Clocking R5532V002
m e
CK-410M+ PG 34 ~ 35
68 PIN CARDBUS Module
33MHz, 3.3V PCI
PG 8
ANT
a id
PCIE x1 Lane 1 52P
USB 0,1,2,3
PG 45,46 USB 0,1,2,3 USB 6 Mini PCIE CONN. Wireless LAN
ANT PG 37
USB4 PG 37
PG 38
S f
Bluetooth
AUDIO PG 46
ICH7-M Golan
Audio 652 BGA PCIE x1 Lane 2
ANT
AZALIA AZALIA Primary USB 7 52P
AMP
Codec
Mini PCIE CONN. WIBRO
AD1986A 12P PG 37
PG 37
n
PG 39 PG 38
AZALIA
AZALIA Secondary
RJ11 MDC PG 20 ~ 23 PCI or PCIE
B B
RJ45
HP & SPDIF. Modem
o
PG 45
MIC-IN PG 45 PG 45
PG 40
FWH
C
2P 2P
82802AC
PG 24
HDD SATA
PG 41
S-ATA
PG 46
SPKR R
Touch
Pri. IDE master PATA 3.3V LPC, 33MHz
MICOM PAD
PG 41
HDD Hitachi H8S
U-ATA 100
Pri. IDE slave
HD64F2169/2160
SPKR L KBD
PG 42 PG 46
A A
PG 41
CD-ROM SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
Power Diagram
D
KBC3_LANPWRON KBC3_SUSPWR KBC3_PWRON KBC3_VRON VCCP3_PWRGD D
AC Adapter YONAH VCC_CORE
P1.05V_AUX P1.05V CALISTOGA
(VCCP) ICH7-M
YONAH
ICH7-M
DOCK DC VDC * Made by ICH7-M Internal VR
(P3.3V_AUX, INTVRMEN high)
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*ICH7-M Sequence SODIMM (DDR II)
P1.8V_AUX P1.8V GPU (NV43M)
P1.05V_Sus GDDR
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P3.3V_Sus SODIMM (DDR II)
Battery DC CALISTOGA
P1.2V GPU (NV43M)
u ti
* Intel used 0.9V_AUX for DDR-2
(LT validation)
P0.9V DDR II-Termination
s n
C DDR II for PEG (TBD) C
MICOM_P3V
MICOM
m e
ICH7-M PCMCIA HDD
CRT USB M_PCI
P5V_AUX P5V MICOM PS/2 PEG
HEATSINK FAN CIRCUIT
a id
R5C841
DDR2 Power VRM
CALISTOGA Thermal Sensor
S f
MICOM
ICH7-M SODIMM R5C841
P3.3V_LAN P3.3V CK410-M FWH M_PCI
SUPER I/O PCMCIA
PEG LEDs
LAN 82573L TPM LCD
CALISTOGA
P2.5V_LAN P2.5V ICH7-M
P3.3V_AUX
n
R5C841
ICH7-M GPU(NV43M)
B LAN 82573L B
LAN
MDC
o
BT
P1.2V_LAN P1.5V VCCA YONAH
P1.5V
CALISTOGA
LAN 82573L ICH7-M
C
GPU (NV43M)
Rail
+V*Always +V*AUX +V SUSPWR PWRON VRON
State GFX_CORE GPU NV43M : P1.0V - P1.2V
Full On ON ON ON H H H
S3 ON ON OFF H L L
S4 ON ON OFF H L L
S5 ON OFF OFF L L L
S5 / S4 S3 S0
A A
SAMSUNG
ELECTRONICS
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
POWER SEQUENCE Rev. 0.8
16
1 11) P3.3V
CLOCK 16) CLK3_PWRGD*
D
2 Thermal D
VDC RTC 1-2) CHP3_RTCRST
Monitor CHIP 17 17) Clock Running
SI4435 Battery Sheet 12
Sheet 8
2) VDC Sheet 20 18) VRM3_CPU_PWRGD
Sheet47
3) MICOM_P3V
3 P3.3V_LAN & P5V_AUX
CPU 16) CLK3_PWRGD*
13) KBC3_PWRGD
POWER RHU002N06 MAX 1999 VRM 16) VRM3_CPU_PWRGD
(KBC3_RST*) SC452 15) VCC_CORE
(1/2) P3.3V_AUX
15
g l
S/W Sheet48
13) KBC3_PWRGD (MICOM_P3V) 14 Sheet 47
Sheet44
DC/DC B'd INTVRMEN
19 CPU
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5 17 17) KBC3_PWRGD
VRMPWRGD
PWROK
5) POWER_SW*
20) PLT3_RST* 19) CPU1_PWRGDCPU 19) CPU1_PWRGDCPU
19
u ti
20) PLT3_RST* 11) P1.5V
9 9) CHP3_SLPS5*/S3*
9 20 20) PCI3_RST* 12) P1.05V
21
KBC 8) KBC3_RSMRST**
s n
C 8 7) P3.3V_AUX 12) ICH_CORE (P1.05V)
Sheet 9-11
C
22) CPU1_CPURST*
7) P1.05V_AUX
10) KBC3_PWRON 10-1) KBC3_VRON 11) P2.5V 11) P2.5V Sheet 13 - 17
10 11) P3.3V 11) P1.5V
ICH7-M
m e
6) KBC3_SUSPWRON 20) PLT3_RST* GMCH
6 Sheet 20-23
7 20 7) P1.8V_AUX
a id
KBC Sub B'd
KBC3_LANPWRON 11) P0.9V
3-1
P1.5V & VCCP 11) P1.5V
12 18
S f
**Note 5-1) KBC3_ALWON(BAT MODE) 12) P1.05V (VCCP) 12) MCH_CORE
*KBC3_ALWON WILL BE HIGH
10) KBC3_PWRON ISL6227 1.5V_PWRGD
AFTER POWER _SW IS PUSHED IN BATT. MODE
14) VCCP3_PWRGD 11) P3.3V
Sheet 45
10-1) KBC3_VRON
P5V_AUX & P3V_AUX
6) KBC3_SUSPWRON
DDR2
MAX 1999 DDR2 POWER 7) P1.8V_AUX and MEM1_VREF 7) P1.8V_AUX
Memory
n
7) P5V_AUX
4 (2/2) MAX8550
11) 0.9V ( or 7) 0.9V_AUX ) 11) P0.9V
Sheet 18 - 19
B 4) P3.3V_LAN
Sheet44 7 11) P5V B
o
1.8V_AUX_PWRGD 20) PLT3_RST*
Sheet 46
6) KBC3_SUSPWRON 11) P1.8V
4) P3.3V_LAN
FDS6680A
11 G73M
7) P3.3V_AUX
7) P5V_AUX 11) P2.5V
C
10) KBC3_PWRON* SI4435DY 11) P5V Ext.GPU
7 Sheet 48 11) GFX_CORE
4) P3.3V_LAN 7) P3.3V_LAN
11) P3.3V 11) P1.2V
FDS6680A Sheet 25 - 28
Sheet 48
4) P1.2V_LAN/1.8V Sheet 40
7) P3.3V_AUX 11) P2.5V 11) P1.8V GDDR
LOM 4) P2.5V_LAN
4 11) P1.5V Sheet 30 - 31
SC338A 11) P1.2V
BCM5751/4401 10) KBC3_PWRON
Sheet 48 11) P3.3V
Sheet 43-44
4) P2.5V_LAN
7) P1.8V_AUX 11) P1.8V MiniPCI
10) KBC3_PWRON FDS6680A 20) PCI3_RST* CardBus
Sheet 48 Sheet 34-35
A A
2) VDC Ext. GPU CORE 11
SC470 11) GFX_CORE SAMSUNG
ELECTRONICS
10) KBC3_PWRON
10 GFx board
4 3 2 1
4 3 2 1
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
POWER RAILS ANALYSIS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG. Rev. 0.8 S0 - S5
S0 - S3
OFF IN S3 - S5
D D
220V
This sheet should be updated !!!
Adapter Battery
3.3V_AUX ( TBD A )
5V_AUX ( TBD A )
MICOM 3V ( TBD A )
1.8V ( TBD A )
CPU CORE ( TBD A )
1.05V ( TBD A )
1.05V
CPU CORE
1.05V (VCCP)
1.5V
g l
n a
0.1 A (TBD)
28A
2.5A
ITP
Yonah-2M
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