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5 4 3 2 1
CZC Confidential
D
CZC Digital technologies Co.,LTD
Board name: Mother Board Schematic 1. System Block Diagram & Schematic page description;
2. Power Block Diagram & Discription;
Project name: CPL S01 (R48)
3. Annotations & information;
Version: VerC
4. Schematic modify Item and history;
Start Date:JAN 6,2010 5. Power on & off Sequence;
C 6. ACPI Mode Switch Timings;
VerA Release Data:
7. Power On Sequence Map;
8. CLOCK Distribution;
B
Hardware drawing by: Hardware check by: EMI Check by:
Power drawing by: Power check by:
A Manager Sign by: A
CZC Technology zw
Title
Size Project Name Rev
A4 R48 C
Date: Thursday, April 22, 2010 Sheet 1 of 56
5 4 3 2 1
S45 System Block Ver:A
PWR_BTN Board
MB
RJ45 Board
D DDR3 1GB/512M
D
QKey & LID Board
LVDS SO-DIMM 0
DDRIII
VGA +V1.5,+V0.75S
Madison/Park PCIE X16 Arrandale
HDMI
SO-DIMM 1
DDRIII To RJ45
+V1.5,+V0.75S
TFT MUX FDI DMI X4
PWR Switch
LVDS PCIE X1 LAN Controller R5538/TPS2231/OZ2709
VGA
MUX AR8131M
VGA
PCIE X1
MUX USB2.0 Express Card
HDMI HDMI
PCIE X1
PCIE X1 mini PCIE Card
3G
C PCH
USB2.0 C
HM55/HM57
SIM SLOT
SATA
ODD
mini PCIE
SATA USB2.0 Card
HDD
2.5" R
USB AUDIO Board
SPI AZALIA LINK Azalia Codec
AN12948A
ALC662
SATA
L
HP Out
BIOS Mic In
LPC BUS
USB2.0
USB
Port
B SPI KB Ctrl & EC B
WPC8763L SD/MS/MS Pro CARD
USB2.0 Cardreader
UB6238N USB
EC Code Port
+
USB2.0 eSATA
USB Port
KB Matrix
USB2.0 Camera
USB2.0 BT
LED
TP
A A
CZC Technology zw
Title
<Title>
Size Project Name Rev
A4 R48 C
Date:
Thursday, April 22, 2010 Sheet
2 of
56
5 4 3 2 1
AC Mode Battery Mode
POWER RAIL
S0 S1 S3 S4 S5 S0 S1 S3 S4 S5
+V3.3AUX ON ON ON ON ON ON ON ON OFF OFF
+V5AUX ON ON ON ON ON ON ON ON OFF OFF
+V1.5 ON ON ON OFF OFF ON ON ON OFF OFF
D D
+V0.75S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V5S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V3.3S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.5S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.8S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.5S ON ON OFF OFF OFF ON ON OFF OFF OFF
+V1.1S ON ON OFF OFF OFF ON ON OFF OFF OFF
+Vcore ON ON OFF OFF OFF ON ON OFF OFF OFF
GFXCORE ON ON OFF OFF OFF ON ON OFF OFF OFF
14.31818MHz 25MHz
XTAL XTAL
C C
133MHz
BCLK
133MHz 100MHz
BCLK DMI
CPU
120MHz
DP
100MHz
DMI
PCH
100MHz
Buffered PEG A
CK505 100MHz Mode GPU
SATA
100MHz
96MHz PCIE NEW CARD
DOT Mini PCIE SLOT X2
B B
14.31818MHz 33MHz
REF PCI
KBC
100MHz
PCIE
LAN
48MHz
25MHz
XTAL
A No stuff A
CZC Technology zw
Title
<Title>
Size Project Name Rev
A3 R48 C
Date: Thursday, April 22, 2010 Sheet 3 of 56
5 4 3 2 1
Board stack up description
Voltage Rails +Vcore:0.75V-1.1V I2C SMB Address PCB Layers
+VDC Primary DC system power supply(9V-12V)
Device Address Hex(W/R) Bus Master Top(Signal1)
D D
+VCC_core Core/VTT voltage for processor Clock Generator 1101 001x D2H/D3H Ground
SO-DIMM0 1010 000x 0xA0 SMB_CLK/DATA PCH Signal2
+V1.8S 1.8V For PCH CPU
SO-DIMM1 1010 010x 0xA4 Signal3 Trace Impedence:50ohm +/-15%
+V1.1S 1.05V /1.1V For PCH CPU GPU
OZ8805LN 0001 011x 16H/17H EC_I2C_CLK2/DATA2 Power
+V0.75S 0.75V DDRIII Termination voltage
EC
+V1.5S 1.5V for system power Thermal Diode G781 1001 100x 98H/99H EC_I2C_CLK/DATA Signal4
Ground
+V1.5 1.5V power rail for DDRIII
Bottom(Signal5)
+V3.3AUX 3.3V always on power rail
+V3.3S 3.3V main power rail
+V5AUX 5V always on power rail
PCB Layer Difference signal Impedence list
+V5S 5V main power rail
C C
USB signal difference impedence 85ohm
LVDS signal difference impedence 85ohm
DDRIII signal difference impedence 85ohm
Power States DDRIII CLK signal difference impedence 68ohm
signal PM_SLP_S3#
state PM_SLP_S4# +V*AUX +V* +V*S CLOCKS
Full ON HIGH ON ON ON ON
S1M(Power On Suspend) HIGH ON ON ON LOW Wake up Events
S3(Suspend to RAM) HIGH LOW ON ON OFF OFF
S4(Suspend to DISK) LOW LOW ON OFF OFF OFF Wake Events State Supported(AC)
S5/Soft Off OFF OFF
With AC IN LOW LOW ON OFF
G3
With Battery LOW LOW OFF OFF OFF OFF
LID switch from EC S3 support
B Power Button from EC S3,S4,S5 support B
Keyboard from EC No
USB device No
[Option]:ns -- Component marked "ns" is not stuff
[Use State]:new --Component Marked "new" is new Materiel.
PCB Footprints
3 5 4
SOT23 SOT23_5
1 2 1 2 3
A A
CZC Technology zw
Title
<Title>
Size Project Name Rev
A3 R48 C
Date: Thursday, April 22, 2010 Sheet 4 of 56
5 4 3 2 1
+V3.3AUX 13,14,15,16,17,19,21,22,24,25,27,28,29,30,31,32,34,35
+V1.5S 7,16,21,22,28,35,36
+V1.5 7,8,10,11,33,35
+V1.1S_VTT 7,12,16,17,35,36
+V3.3S 9,10,11,12,13,14,15,16,17,18,19,20,21,22,24,25,27,28,29,34,35,36,37,38,48
U1A
+V1.5S_CPU 7
PEG_ICOMPI B26 PEG_IRCOMP_R R1 49.9,1%
PEG_ICOMPO A26 PEG_RXN[15:0] 41
A24 B27 PEG_RXN0
14 DMI_TXN0 DMI_RX#[0] PEG_RCOMPO
C23 A25 EXP_RBIAS R2 750 PEG_RXN1
14 DMI_TXN1 DMI_RX#[1] PEG_RBIAS
B22 PEG_RXN2
14 DMI_TXN2 DMI_RX#[2]
A21 K35 PEG_RXN15 PEG_RXN3
14 DMI_TXN3 DMI_RX#[3] PEG_RX#[0]
J34 PEG_RXN14 PEG_RXN4
PEG_RX#[1] PEG_RXN13 PEG_RXN5
14 DMI_TXP0 B24 DMI_RX[0] PEG_RX#[2] J33
D23 G35 PEG_RXN12 PEG_RXN6
14 DMI_TXP1 DMI_RX[1] PEG_RX#[3]
DMI
B23 G32 PEG_RXN11 PEG_RXN7
14 DMI_TXP2 DMI_RX[2] PEG_RX#[4]
A22 F34 PEG_RXN10 PEG_RXN8
14 DMI_TXP3 DMI_RX[3] PEG_RX#[5]
F31 PEG_RXN9 PEG_RXN9
PEG_RX#[6] PEG_RXN8 PEG_RXN10
D D24 DMI_TX#[0] PEG_RX#[7] D35 D
14 DMI_RXN0 PEG_RXN7 PEG_RXN11
G24 DMI_TX#[1] PEG_RX#[8] E33
14 DMI_RXN1 PEG_RXN6 PEG_RXN12
F23 DMI_TX#[2] PEG_RX#[9] C33
14 DMI_RXN2 PEG_RXN5 PEG_RXN13
H23 DMI_TX#[3] PEG_RX#[10] D32
14 DMI_RXN3 PEG_RXN4 PEG_RXN14
PEG_RX#[11] B32
D25 C31 PEG_RXN3 PEG_RXN15
14 DMI_RXP0 DMI_TX[0] PEG_RX#[12] PEG_RXN2
F24 DMI_TX[1] PEG_RX#[13] B28 PEG_RXP[15:0] 41
14 DMI_RXP1 PEG_RXN1 PEG_RXP0
E23 DMI_TX[2] PEG_RX#[14] B30
14 DMI_RXP2 PEG_RXN0 PEG_RXP1
G23 DMI_TX[3] PEG_RX#[15] A31
14 DMI_RXP3 PEG_RXP2
J35 PEG_RXP15 PEG_RXP3
PEG_RX[0] PEG_RXP14 PEG_RXP4
PEG_RX[1] H34
H33 PEG_RXP13 PEG_RXP5
14 FDI_TXN[7:0] FDI_TXN0 PEG_RX[2] PEG_RXP12 PEG_RXP6
E22 FDI_TX#[0] PEG_RX[3] F35
FDI_TXN1 D21 G33 PEG_RXP11 PEG_RXP7
FDI_TXN2 FDI_TX#[1] PEG_RX[4] PEG_RXP10 PEG_RXP8
D19 FDI_TX#[2] PEG_RX[5] E34
FDI_TXN3 D18 F32 PEG_RXP9 PEG_RXP9
FDI_TXN4 FDI_TX#[3] PEG_RX[6] PEG_RXP8 PEG_RXP10
G21 FDI_TX#[4] PEG_RX[7] D34
FDI_TXN5 E19 F33 PEG_RXP7 PEG_RXP11
FDI_TXN6 FDI_TX#[5] PEG_RX[8] PEG_RXP6 PEG_RXP12
F21 FDI_TX#[6] PEG_RX[9] B33
PCI EXPRESS -- GRAPHICS
FDI_TXN7
Intel(R) FDI
G18 D31 PEG_RXP5 PEG_RXP13
FDI_TX#[7] PEG_RX[10] PEG_RXP4 PEG_RXP14
PEG_RX[11] A32
C30 PEG_RXP3 PEG_RXP15
14 FDI_TXP[7:0] FDI_TXP0 PEG_RX[12] PEG_RXP2
D22 FDI_TX[0] PEG_RX[13] A28
FDI_TXP1 C21 B29 PEG_RXP1
FDI_TXP2 FDI_TX[1] PEG_RX[14] PEG_RXP0
D20 FDI_TX[2] PEG_RX[15] A30 lane reversal
FDI_TXP3 C18 FDI_TX[3] PEG_TXN[15:0] 41
FDI_TXP4 G22 L33 C1 0.1uF/16V,X7R DGPU PEG_TXN15 PEG_TXN0
FDI_TXP5 FDI_TX[4] PEG_TX#[0] C2 0.1uF/16V,X7R DGPU PEG_TXN14 PEG_TXN1
E20 FDI_TX[5] PEG_TX#[1] M35
FDI_TXP6 F20 M33 C3 0.1uF/16V,X7R DGPU PEG_TXN13 PEG_TXN2
FDI_TXP7 FDI_TX[6] PEG_TX#[2] C4 0.1uF/16V,X7R DGPU PEG_TXN12 PEG_TXN3
G19 FDI_TX[7] PEG_TX#[3] M30
L31 C5 0.1uF/16V,X7R DGPU PEG_TXN11 PEG_TXN4
PEG_TX#[4] C6 0.1uF/16V,X7R DGPU PEG_TXN10 PEG_TXN5
14 FDI_FSYNC0 F17 FDI_FSYNC[0] PEG_TX#[5] K32
E17 M29 C7 0.1uF/16V,X7R DGPU PEG_TXN9 PEG_TXN6
14 FDI_FSYNC1 FDI_FSYNC[1] PEG_TX#[6]
J31 C8 0.1uF/16V,X7R DGPU PEG_TXN8 PEG_TXN7
PEG_TX#[7] C9 0.1uF/16V,X7R DGPU PEG_TXN7 PEG_TXN8
14 FDI_INT C17 FDI_INT PEG_TX#[8] K29
H30 C10 0.1uF/16V,X7R DGPU PEG_TXN6 PEG_TXN9
PEG_TX#[9] C11 0.1uF/16V,X7R DGPU PEG_TXN5 PEG_TXN10
14 FDI_LSYNC0 F18 FDI_LSYNC[0] PEG_TX#[10] H29
D17 F29 C12 0.1uF/16V,X7R DGPU PEG_TXN4 PEG_TXN11
14 FDI_LSYNC1 FDI_LSYNC[1] PEG_TX#[11]
E28 C13 0.1uF/16V,X7R DGPU PEG_TXN3 PEG_TXN12
PEG_TX#[12] C14 0.1uF/16V,X7R DGPU PEG_TXN2 PEG_TXN13
PEG_TX#[13] D29
D27 C15 0.1uF/16V,X7R DGPU PEG_TXN1 PEG_TXN14
PEG_TX#[14] C16 0.1uF/16V,X7R DGPU PEG_TXN0 PEG_TXN15
PEG_TX#[15] C26
PEG_TXP[15:0] 41
L34 C17 0.1uF/16V,X7R DGPU PEG_TXP15 PEG_TXP0
PEG_TX[0] C18 0.1uF/16V,X7R DGPU PEG_TXP14 PEG_TXP1
PEG_TX[1] M34
M32 C19 0.1uF/16V,X7R DGPU PEG_TXP13 PEG_TXP2
PEG_TX[2] C20 0.1uF/16V,X7R DG</pre><br><br>
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