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Global LCD Panel Exchange Center www.panelook.com
Document Version: 8
Date: 2005/3/4
Product Functional Specification
15 inch XGA Color TFT LCD Module
Model Name : B150XG02 V.3
( ) Preliminary Specification
( ) Final Specification
Note: This Specification is subject to change without notice.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
1/1
No Reproduction and Redistribution Allowed.
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I. Contents
1.0 Handling Precautions
2.0 General Description
2.1 Characteristics
2.2 Functional Block Diagram
3.0 Absolute Maximum Ratings
4.0 Optical Characteristics
5.0 Signal Interface
5.1 Connectors
5.2 Signal Pin
5.3 Signal Description
5.4 Signal Electrical Characteristics
5.5 Signal for Lamp Connector
5.6 Inverter Characteristic
6.0 Pixel Format Image
7.0 Parameter Guide Line for CCFL Inverter
8.0 Interface Timings
8.1 Timing Characteristics
8.2 Timing Definition
9.0 Power Consumption
10.0 Power ON/OFF Sequence
11.0 Mechanical Characteristics
12.0 EDID Table
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
2/2
No Reproduction and Redistribution Allowed.
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II Record of Revision
Version and Page Old description New Description Remark
Date
0.1. 2004/8/16 All First Edition for Customer All
0.2. 2004/10/13 15 Update inverter spec.
0.2. 2004/10/13 6 Luminance average (5pts) Luminance average (5pts)
170nit 180nit
0.2. 2004/10/13 6 Add luminance min (5pts)
150nit
0.3. 2005/1/17 15 Update inverter output current
0.3. 2005/1/17 16 Min. ICFL 3.0mA Min. ICFL 2.0mA
0.4 2005/2/25 6 -20 to +60 -25 to +65 Storage
Temperature
0.4 2005/2/25 8 -20 to +60 -25 to +65 Storage
Temperature
0.4 2005/2/25 9 N/A 150 min White
Luminance
(CCFL 6.0 mA)
0.4 2005/2/25 11 LVDS differential data input LVDS differential data input Signal
(Blue2-Blue5, Hsync, Vsync, (Blue2-Blue5, DSPTMG) Description
DSPTMG)
0.4 2005/2/25 15 549 (min), 610 (typ), 585 (min), 650 (typ), 715(max) Output voltage
671(max)
0.4 2005/2/25 16 N/A 150 min White
Luminance
5 points
average
0.4 2005/2/25 17 With Hsync, Hsw, Hbp,Hfp, Deleted Hsync, Hsw, Hbp,Hfp, Timing
Vw, Vfp and Vbp Vw, Vfp and Vbp Characteristics
0.4 2005/2/25 18 With Hsync & Vsync Deleted Hsync & Vsync Timing
Definition
0.4 2005/2/25 18 With VDDrp & VDDns Deleted VDDrp & VDDns Power
Consumption
0.4 2005/3/1 23 Add EDID Table
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
3/3
No Reproduction and Redistribution Allowed.
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1.0 Handing Precautions
1) Since front polarizer is easily damaged, pay attention not to scratch it.
2) Be sure to turn off power supply when inserting or disconnecting from input connector.
3) Wipe off water drop immediately. Long contact with water may cause discoloration or
spots.
4) When the panel surface is soiled, wipe it with absorbent cotton or other soft cloth.
5) Since the panel is made of glass, it may break or crack if dropped or bumped on hard
surface.
6) Since CMOS LSI is used in this module, take care of static electricity and insure
human earth when handling.
7) Do not open nor modify the Module Assembly.
8) Do not press the reflector sheet at the back of the module to any directions.
9) In case if a Module has to be put back into the packing container slot after once it was
taken out from the container, do not press the center of the CCFL Reflector edge.
Instead, press at the far ends of the CFL Reflector edge softly. Otherwise the TFT
Module may be damaged.
10) At the insertion or removal of the Signal Interface Connector, be sure not to rotate nor
tilt the Interface Connector of the TFT Module.
11) After installation of the TFT Module into an enclosure (Notebook PC Bezel, for
example), do not twist nor bend the TFT Module even momentary. At designing the
enclosure, it should be taken into consideration that no bending/twisting forces are
applied to the TFT Module from outside. Otherwise the TFT Module may be damaged.
12) Cold cathode fluorescent lamp in LCD contains a small amount of mercury. Please follow
local ordinances or regulations for disposal.
13) Small amount of materials having no flammability grade is used in the LCD module. The
LCD module should be supplied by power complied with requirements of Limited Power
Source(2.11, IEC60950 or UL1950), or be applied exemption.
14) The LCD module is designed so that the CFL in it is supplied by Limited Current Circuit(2.4,
IEC60950 or UL1950). Do not connect the CFL in Hazardous Voltage Circuit.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
4/4
No Reproduction and Redistribution Allowed.
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2.0 General Description
This specification applies to the 15.0 inch Color TFT/LCD Module B150XG02 V.3.
This module is designed for a display unit of notebook style personal computer.
The screen format is intended to support the XGA (1024(H) x 768(V)) screen and 262k
colors (RGB 6-bits data driver).
All input signals are LVDS interface compatible.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
5/5
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2.1 Display Characteristics
The following items are characteristics summary on the table under 25 condition:
ITEMS Unit SPECIFICATIONS
Screen Diagonal [mm] 381
Active Area [mm] 304.1 X 228.1
Pixels H x V 1024(x3) x 768
Pixel Pitch [mm] 0.297X0.297
Pixel Arrangement R.G.B. Vertical Stripe
Display Mode Normally White
Typical White Luminance [cd/m2] 180 (5 point average)
(ICFL=6.0mA) 150 (5 point min.)
Luminance Uniformity 1.25 max. (5 pts)
1.65 max. (13pts)
Contrast Ratio 300 typ.
Optical Rise Time/Fall Time [msec] 16/9
Nominal Input Voltage VDD [Volt] +3.3 typ.
Typical Power Consumption [Watt] 6.3W Max (w/o Inverter, All black
(VDD line + VCFL line) pattern)@LCM circuit 2.1 (Max.),B/L
input 4.2 (Max.)
Weight (Panel+Inverter) [Grams] 600g max.
Physical Size [mm] 317.3 x 242.0 x 6.5 max.
Electrical Interface 1 channel LVDS
Support Color Native 262K colors ( RGB 6-bit data
driver )
Temperature Range
Operating [oC] 0 to +50
Storage (Shipping) [oC] -25 to +65
Surface Treatment 3H min
Color Gamut NTSC 42% min
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
6/6
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2.2 Functional Block Diagram
The following diagram shows the functional block of the 15.0 inches Color TFT/LCD
Module:
LCD DRIVE
Backlight Unit
CARD
6bit color data
for R/G/B
LCD
DSPTMG Controller TFT ARRAY/CELL
Vsync
Hsync
1024(R/G/B) x 3
(3 pairs LVDS)
DC-DC
Converter
DTCLK
Ref circuit
(1 pair LVDS)
Y-Driver
VDD
X-Driver
GND
LCD Connector
Lamp Connector
JAE JAE FI-XB30SL-HF10
JST BHSR-02VS-1
Mating Type JAE FI-S30M
Mating Type SM02B-BHSS-1
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
7/7
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3.0 Absolute Maximum Ratings
Absolute maximum ratings of the module is as following:
Item Symbol Min Max Unit Conditions
Logic/LCD Drive Voltage VDD -0.3 +4.0 [Volt]
Input Voltage of Signal Vin -0.3 VDD+0.3 [Volt]
LVDS Input Voltage VLVDS in -0.3 +2.6 [Volt]
CCFL Current ICFL - 7 [mA]
rms
CCFL Ignition Voltage Vs - 1150 Vrms
Operating Temperature TOP 0 +50 [oC] Note 1
Operating Humidity HOP 8 95 [%RH] Note 1
Storage Temperature TST -25 +65 [oC] Note 1
Storage Humidity HST 5 95 [%RH] Note 1
Vibration 1.5 10-500 G Hz 2hr/axis, X,Y,Z
(random)
Shock 220 , 2 G ms Half sine wave
Note 1 : Maximum Wet-Bulb should be 39 and No condensation.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
8/8
No Reproduction and Redistribution Allowed.
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4.0 Optical Characteristics
The optical characteristics are measured under stable conditions as follows under 25
condition:
Item Conditions Typ. Note
Viewing Angle [degree] Horizontal (Right) 40 min. ----
[degree] K = 10 (Left) 40 min.
K: Contrast Ratio [degree]Vertical (Upper) 10 min. --
[degree] K = 10 (Lower) 30 min. --
Contrast ratio 300 typ. 200 min.
Luminance 1.25 max. (5 pts)
Uniformity 1.65 max. (13pts)
Response Time [msec] Rising 16 typ. 24 Max.
(Room Temp.) [msec] Falling 9 typ. 11Max.
Color Red x 0.580+-0.02
Chromaticity Red y 0.340+-0.02
Coordinates (CIE) Green x 0.310+-0.02
Green y 0.550+-0.02
Blue x 0.155+-0.02
Blue y 0.155+-0.02
White x 0.313+-0.02
White y 0.329+-0.02
2
White Luminance [cd/m ] 180 typ. (5 points 150 min
(CCFL 6.0 mA) average)
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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5.0 Signal Interface
5.1 Connectors
Physical interface is described as for the connector on module.
These connectors are capable of accommodating the following signals and will be following
components.
Connector Name / Designation For Signal Connector
Manufacturer JAE or compatible
Type / Part Number JAE FI-XB30SL-HF10
Mating Housing/Part Number FI-X30M, FI-X30C or FI-X30H
Mating Contact/Part Number FI-C3-A1
Connector Name / Designation For Lamp Connector
Manufacturer JST
Type / Part Number BHSR-02VS-1
Mating Type / Part Number SM02B-BHSS-1-TB
5.2 Signal Pin
Pin# Signal Name Pin# Signal Name
1 GND 2 VDD
3 VDD 4 VEDID
5 BIST Test 6 CLKEDID
7 DATAEDID 8 RxIN0-
9 RxIN0+ 10 GND
11 RxlN1- 12 RxlN1+
13 GND 14 RxIN2-
15 RxIN2+ 16 GND
17 RxCLKIN- 18 RxCLKIN+
19 GND 20 NC
21 NC 22 NC
23 NC 24 NC
25 NC 26 NC
27 NC 28 NC
29 NC 30 NC
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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5.3 Signal Description
The module using a LVDS receiver. LVDS is a differential signal technology for LCD interface
and high speed data transfer device. Transmitter shall be SN75LVDS84 (negative edge
sampling) or compatible.
Signal Name Description
RxIN0-, RxIN0+ LVDS differential data input(Red0-Red5, Green0)
RxIN1-, RxIN1+ LVDS differential data input(Green1-Green5, Blue0-Blue1)
RxIN2-, RxIN2+ LVDS differential data input(Blue2-Blue5, DSPTMG)
RxCLKIN-, RxCLKIN0+ LVDS differential clock input
VDD +3.3V Power Supply
GND Ground
Note: Input signals shall be low or Hi-Z state when VDD is off.
Internal circuit of LVDS inputs are as following.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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Signal Input
SN75LVDS86 or Compatible
Pin No.
8 RxIN0-
R
9 RxIN0+
11 RxIN1-
R
12 RxIN1+
14 RxIN2-
R
15 RxIN2+
17 RxCLKIN-
R
18 RxCLKIN+
The module uses a 100ohm resistor between positive and negative data lines of
each receiver input
Signal Name Description
RED5 Red Data 5 (MSB) Red-pixel Data
RED4 Red Data 4 Each red pixel's brightness data consists of
RED3 Red Data 3 these 6 bits pixel data.
RED2 Red Data 2
RED1 Red Data 1
RED0 Red Data 0 (LSB)
Red-pixel Data
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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GREEN 5 Green Data 5 (MSB) Green-pixel Data
GREEN 4 Green Data 4 Each green pixel's brightness data consists of
GREEN 3 Green Data 3 these 6 bits pixel data.
GREEN 2 Green Data 2
GREEN 1 Green Data 1
GREEN 0 Green Data 0 (LSB)
Green-pixel Data
BLUE 5 Blue Data 5 (MSB) Blue-pixel Data
BLUE 4 Blue Data 4 Each blue pixel's brightness data consists of
BLUE 3 Blue Data 3 these 6 bits pixel data.
BLUE 2 Blue Data 2
BLUE 1 Blue Data 1
BLUE 0 Blue Data 0 (LSB)
Blue-pixel Data
DTCLK Data Clock The typical frequency is 65.0 MHZ.. The signal
is used to strobe the pixel data and DSPTMG
signals. All pixel data shall be valid at the falling
edge when the DSPTMG signal is high.
DSPTMG Display Timing This signal is strobed at the falling edge of
-DTCLK. When the signal is high, the pixel data
shall be valid to be displayed.
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
5.4 Signal Electrical Characteristics
Input signals shall be low or Hi-Z state when VDD is off.
It is recommended to refer the specifications of SN75LVDS86DGG(Texas Instruments) in
detail.
Signal electrical characteristics are as follows;
Symbol Parameter Condition Min Max Unit
Differential Input High Vcm=+1.2V
VTH Threshold 100 [mV]
Differential Input Low Vcm=+1.2V
VTL Threshold -100 [mV]
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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LVDS Macro AC characteristics are as follows:
Min. Max.
Clock Frequency (T) 50MHZ 68MHZ
Data Setup Time (Tsu) 600ps
Data Hold Time (Thd) 600ps
T
Input Clock
Input Data
Tsu Thd
5.5 Signal for Lamp connector
Pin # Signal Name
1 Lamp High Voltage
2 Lamp Low Voltage
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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5.6 Inverter Characteristic
. Item Symbol Condition Min. Typ. Max. Uint
1 Input Voltage Vin 7.5 14.4 21 V
2 Input Current Iin Vin=7.5V,SMData=00H 590 650 710 mA
3 Input Power Pin Vin=7.5V,SMData=00H 5.25 W
Input Signal Level for
4 4.85 5 5.2 V
5VSUS,5VALW
Backlight ON FPVEE=Hi 2.0 - 5.25 V
5
ON/OFF Control OFF FPVEE=Lo -0.3 - 0.8 V
Brightness Adjust (Lamp
6 SMData Control by SMBus FFH - 00H -
Current Control)
7 Output Voltage Vout SMData=00H 585 650 715 V(rms)
Vin(7.5V~21V)SMData=FFH Ta=25 % duty
Duty cycle 6 10 14
, after running 30 min. cycle
8 Output Current
Vin(7.5V~21V)SMData=00H Ta=25
Iout (Max) 5.7 6.0 6.3 mA(rms)
, after running 30 min.
9 Frequency Freq Vin=7.5~21V 45 55 65 KHz
10 Output Power Pout Vin=21V,SMData=00H --- 4.4 4.6 W
11 Open Lamp Voltage Vopen No Load 1400 - 1800 V(rms)
12 Striking Time Ts Vin=7.5V~21V 0.6 1 1.4 Sec
Vin=7.5V, Iout=Max.
13 Efficiency 80 --- --- %
Load=110Kohm//15 p farad
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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6.0 Pixel Format Image
Following figure shows the relationship of the input signals and LCD pixel format.
VW /LQH 5 * % 5 * % 5 * % 5 * %
KW /LQH 5 * % 5 * % 5 * % 5 * %
7.0 Parameter guide line for CCFL Inverter
Parameter Min DP-1 Max Units Condition
White Luminance
5 points average 150 180 [cd/m2 ] (Ta=25 )
CCFL current(ICFL) 2.0 6.0 7.0 [mA] (Ta=25 )
rms Note 2
CCFL Frequency(FCFL) 40 50 60 [KHz] (Ta=25 )
Note 3
CCFL Ignition Voltage(Vs) 1,150 [Volt] (Ta= 0 )
rms Note 4
CCFL Voltage (Reference) 700 [Volt] (Ta=25 )
(VCFL) rms Note 5
CCFL Power consumption 4.6 [Watt] (Ta=25 )
(PCFL) Note 5
Note 1: DP-1 are AUO recommended Design Points.
(C) Copyright AU Optronics, Inc.
August, 2001 All Rights Reserved. B150XG02 V.3 Ver.8
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*1 All of characteristics listed are measured under the condition using the AUO Test inverter.
*2 In case of using an inverter other than listed, it is recommended to check the inverter
carefully. Sometimes, interfering noise stripes appear on the screen, and substandard
luminance or flicker at low power may happen.
*3 In designing an inverter, it is suggested to check safety circuit ver carefully. Impedance of
CFL, for instance, becomes more than 1 [M ohm] when CFL is damaged.
*4 Generally, CFL has some amount of delay time after applying kick-off voltage. It is
recommended to keep on applying kick-off voltage for 1 [Sec] until discharge.
*5 CFL discharge frequency must be carefully chosen so as not to produce interfering noise
stripes on the screen.
*6 Reducing CFL current increases CFL discharge voltage and generally increases CFL
discharge frequency. So all the parameters of an inverter should be carefully designed so as
not to produce too much leakage current from high-voltage output of the inverter.
Note 2: It should be emplyed the inverter which has "Duty Dimming", if ICFL is less than 4mA.
Note 3: CFL discharge frequency should
be carefully determined to avoid interference between inverter and TFT LCD.
Note 4: CFL inverter should be able to give out a power that has a generating capacity of over
1,400 voltage. Lamp units need 1,400 voltage minimum for ignition.
Note 5: Calculator value for reference (ICFL◦ Jabse Service Manual Search 2026 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo