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PROPRIETARY NOTE
THIS SPECIFICATION IS THE PROPERTY OF BOE DT AND SHALL NOT BE
REPRODUCED OR COPIED WITHOUT THE WRITTEN PERMISSION OF BOE DT
AND MUST BE RETURNED TO BOE DT UPON ITS REQUEST
TITLE:
HV460WU2-202 Preliminary Product Specification
BEIJING BOE DISPLAY TECHNOLOGY
SPEC. NUMBER PRODUCT GROUP REV. ISSUE DATE PAGE
S8XX-XXXX TFT LCD P1 2012.04.28 1 of 26
B2010-8002-O (1/3) A4(210 X 297)
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REVISION HISTORY
REV. ECN NO. DESCRIPTION OF CHANGES DATE PREPARED
P0 - Initial Release 2012.02.17 Hongming Zhan
P1 - 3D Optical Spec Added 2012.04.28 Hongming Zhan
Packing Method : 6 Inner Box/100Pcs/
- 2012.04.28 Hongming Zhan
1 Pallet 5 Inner Box/100Pcs/1 Pallet
SPEC. NUMBER SPEC. TITLE PAGE
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Contents
No ITEM Page
REVISIONS HISTORY 2
CONTENTS 3
1 GENERAL DESCRIPTION 4
1.1 Introduction
1.2 Features
1.3 Applications
1.4 General Specification
2 ABSOLUTE MAXIMUM RATINGS 6
3 ELECTRICAL SPECIFICATIONS 7
3.1 TFT LCD Open Cell
4 INTERFACE CONNECTION 8
4.1 Open Cell Input Signal & Power
4.2 LVDS Interface
5 SIGNAL TIMING SPECIFICATIONS 11
5.1 Timing Parameters
5.2 Signal Timing Waveform
5.3 Input Signals, Basic Display Colors & Cray Scale Of Colors
5.4 Power Sequence
6 OPTICAL SPECIFICATIONS 15
7 MECHANICAL CHARACTERISTICS 18
8 RELIABLITY 19
9 PRODUCT SERIAL NUMBER 20
10 PACKING INFORMATION 21
11 HANDING & CAUTIONS 23
12 APPENDIX 24
SPEC. NUMBER SPEC. TITLE PAGE
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1.0 GENERAL DESCRIPTION
1.1 Introduction
HV460WU2-202 is a color active matrix TFT LCD open cell using amorphous silicon TFT's
(Thin Film Transistors) as an active switching devices. This module has a 46.00 inch
diagonally measured active area with WUXGA resolutions (1920 horizontal by 1080
vertical pixel array). Each pixel is divided into RED, GREEN, BLUE dots which are
arranged in vertical stripe and this module can display 16.7M colors. The TFT-LCD panel
used for this module is adapted for a low reflection and higher color type.
RGB(Mini-LVDS)
VDD Source Driver Circuit
+12.0V
S1 S1920
G1
CN1
Gate Drive Circuit
LVDS
Timing Controller
2Ports
(51pin)
[LVDS Rx & Mini-LVDS
LVDS_SEL Tx integrated]
#7
TFT - LCD Panel
er
(1920 RGB 1080 pixels)
Power Circuit G1080
Block
1.2 Features
LVDS interface with 2 pixel / clock
High-speed response
Low color shift image quality
8-bit color depth, display 16.7M colors
High luminance and contrast ratio, low reflection and wide viewing angle
DE (Data Enable) only mode
ADS technology is applied for high display quality
RoHS compliant
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1.3 Application
Home Alone Multimedia TFT-LCD TV
Display Terminals for Control System
Full High Definition TV(FHD TV)
AV application Products
1.4 General Specification
< Table 1. General Specifications >
Parameter Specification Unit Remark
Active area 1018.08(H) 572.67(V) mm
Number of pixels 1920(H) 1080(V) pixels
Pixel pitch 176.75(H) RGB 530.25(V)
Pixel arrangement Pixels RGB Vertical stripe
Display colors 16.7M(8bits-true) colors
Display mode Transmission mode, Normally Black
At center
Open Cell
6.2(typ.) % point with
Transmittance
BOE BLU
With T-con
Weight 2440 (Typ.) gram
Board
Power Consumption 9.0(Typ.) Watt
Haze 10%, 3H, Anti-glare treatment
Surface Treatment (Front Polarizer)
Clear (Bottom Polarizer)
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2.0 ABSOLUTE MAXIMUM RATINGS
The followings are maximum values which, if exceed, may cause faulty operation or
damage to the unit. The operational and non-operational maximum voltage and current
values are listed in Table 2.
< Table 2. Open Cell Electrical Specifications > [VSS=GND=0V]
Parameter Symbol Min. Max. Unit Remark
Power Supply Voltage VDD VSS-0.3 13.5 V Ta = 25
TOP 0 +50
Operating Temperature
TSUR 0 +60
Storage Temperature TST -20 +60
Note 1
Operating Ambient
Hop 10 80 %RH
Humidity
Storage Humidity Hst 10 80 %RH
Note 1 : Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be 39 max. and no condensation of water.
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3.0 ELECTRICAL SPECIFICATIONS
3.1 TFT LCD Open Cell
< Table 3. Open Cell Electrical Specifications > [Ta =25 2 ]
Values
Parameter Symbol Unit Remark
Min Typ Max
Power Supply Input Voltage VDD 10.8 12 13.2 Vdc
Power Supply Ripple Voltage VRP 300 mV
Power Supply Current IDD - 750 850 mA
Note 1
Power Consumption PDD 9.0 10.2 Watt
Rush current IRUSH - - 3.0 A Note 2
Differential Input High
VLVTH +100 +300 mV
Threshold Voltage
LVDS
Interface Differential Input Low
VLVTL -300 -100 mV
Threshold Voltage
Common Input Voltage VLVC 1.0 1.2 1.4 V
Input High Threshold
VIH 2.7 - 3.3 V
CMOS Voltage
Interface Input Low Threshold
VIL 0 - 0.6 V
Voltage
Note 1 : The supply voltage is measured and specified at the interface connector of LCM.
The current draw and power consumption specified is for VDD=12.0V,
Frame rate fV=60Hz and Clock frequency = 75.4MHz.
Test Pattern of power supply current
a) Typ : Color Test (L0/L255) b) Max : Vertical Subline (L0/L255)
Note 2 : The duration of rush current is about 2ms and rising time of Power Input is 1ms(min)
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4.0 INTERFACE CONNECTION
4.1 Module Input Signal & Power
- Connector : IS050-C51B-C39-S(UJU)/ FI-RE51S-HF-R1500 (JAE) or Equivalent.
< Table 4. Open Cell Input Connector Pin Configuration >
Pin No Symbol Description Pin No Symbol Description
1 NC No Connection 21 GND Ground
First pixel negative LVDS
2 SDA I2C Data 22 CH1[3]-
differential data input. Pair3
First pixel positive LVDS
3 SCL I2C Clock 23 CH1[3]+
differential data input. Pair3
First pixel negative LVDS
4 NC Not Connected 24 CH1[4]-/NC
differential data input. Pair4
First pixel positive LVDS
5 NC Not Connected 25 CH1[4]+/NC
differential data input. Pair4
6 NC Not Connected 26 NC Not Connected
High or Open: NS
7 SELLVDS 27 NC Not Connected
Low: JEIDA
Second pixel negative LVDS
8 NC Not Connected 28 CH2[0]-
differential data input. Pair0
Second pixel positive LVDS
9 NC Not Connected 29 CH2[0]+
differential data input. Pair0
Second pixel negative LVDS
10 NC Not Connected 30 CH2[1]-
differential data input. Pair1
Second pixel positive LVDS
11 GND Ground 31 CH2[1]+
differential data input. Pair1
First pixel negative LVDS Second pixel negative LVDS
12 CH1[0]- 32 CH2[2]-
differential data input. Pair0 differential data input. Pair2
First pixel positive LVDS Second pixel positive LVDS
13 CH1[0]+ 33 CH2[2]+
differential data input. Pair0 differential data input. Pair2
First pixel negative LVDS
14 CH1[1]- 34 GND Ground
differential data input. Pair1
First pixel positive LVDS
15 CH1[1]+ 35 CH2CLK- First pixel negative LVDS clock
differential data input. Pair1
First pixel negative LVDS
16 CH1[2]- 36 CH2CLK+ First pixel positive LVDS clock
differential data input. Pair2
First pixel positive LVDS
17 CH1[2]+ 37 GND Ground
differential data input. Pair2
Second pixel negative LVDS
18 GND Ground 38 CH2[3]-
differential data input. Pair3
Second pixel positive LVDS
19 CH1CLK- First pixel negative LVDS clock 39 CH2[3]+
differential data input. Pair3
20 CH1CLK+ First pixel positive LVDS clock
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Pin No Symbol Description Pin No Symbol Description
Second pixel negative LVDS
40 CH2[4]-/NC 46 GND Ground
differential data input. Pair4
Second pixel positive LVDS
41 CH2[4]+/NC 47 NC Not Connected
differential data input. Pair4
42 NC Not Connected 48 VCC Input Voltage
43 NC Not Connected 49 VCC Input Voltage
44 GND Ground 50 VCC Input Voltage
45 GND Ground 51 VCC Input Voltage
Notes : 1. NC(Not Connected) : This pins are only used for BOE internal operations.
2. Input Level of LVDS signal is based on the IEA 664 Standard.
3. LVDS_SEL : This pin is used for selecting LVDS signal data format.
If this Pin : High (3.3V) or Open (NC) Normal NS LVDS format
Otherwise : Low (GND) JEIDA LVDS format
Rear view of LCM BIST Pattern
IS050-C51B-C39-S (UJU) or 51
1
FI-RE51S-HF-R1500 (JAE)
SPEC. NUMBER SPEC. TITLE PAGE
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4.2 LVDS Interface
- LVDS Receiver : Timing Controller (LVDS Rx merged) / LVDS Data : Pixel Data
< Table 5. Open Cell Input Connector Pin Configuration >
8-bit LVDS Type
Channel No. Data No.
NS JEIDA
Bit-0 R0 R2
Bit-1 R1 R3
Bit-2 R2 R4
0 Bit-3 R3 R5
Bit-4 R4 R6
Bit-5 R5 R7
Bit-6 G0 G2
Bit-0 G1 G3
Bit-1 G2 G4
Bit-2 G3 G5
1 Bit-3 G4 G6
Bit 4
Bit-4 G5 G7
Bit-5 B0 B2
Bit-6 B1 B3
Bit-0 B2 B4
Bit-1 B3 B5
Bit-2 B4 B6
2 Bit-3 B5 B7
Bit-4 HS HS
Bit-5 VS VS
Bit-6 DE DE
Bit-0 R6 R0
Bit-1 R7 R1
Bit-2 G6 G0
3 Bit-3 G7 G1
Bit-4 B6 B0
Bit-5 B7 B1
Bit-6 -
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5.0 SIGNAL TIMING SPECIFICATION
5.1 Timing Parameters (DE only mode)
< Table 6. Timing Table >
Item Symbols Min Typ Max Unit
Frequency 1/Tc 66.00 74.25 82 MHz
Clock High Time Tch - 4/7Tc -
Low Time Tcl - 4/7Tc -
1116 1126 1150 lines
Frame Period Tv
56.32 60 62.77 Hz
Vertical Display Period Tvd - 1080 - lines
One line Scanning Period Th 1050 1100 1150 clocks
Horizontal Display Period Thd 960 960 960 clocks
Notes: This product is DE only mode. The input of Hsync & Vsync signal does not have an effect on normal
operation.
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5.2 Signal Timing Waveform
tCLK
DCLK 0.5 VDD
Valid data
First data Invalid data Pixel data Pixel data Invalid data
Valid data
Second data Invalid data Pixel data Pixel data Invalid data
DE(Data Enable)
tHP
HSync
tHV
DE(Data Enable)
tVP
VSync
tVV
DE(Data Enable)
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5.3 Input Signals, Basic Display Colors and Gray Scale of Colors
< Table 7. Input Signal and Display Color Table >
Input Data Signal
Color & Gray Scale Red Data Green Data Blue Data
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Green 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Basic Cyan 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Colors Red 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Magenta 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Yellow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Darker 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Gray Scale
of Red
Brighter 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Red 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Gray Scale Darker 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
of Green
Brighter 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0
Green 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Darker 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Gray Scale
of Blue
Brighter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0
Blue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Black 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
Gray Scale Darker 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
of White
Brighter 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0
White 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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5.4 Power Sequence
12V
0.9VDD 0.9VDD
Power Supply 0.1VDD 0.1VDD
VDD 0V
T1
T12
T2 T3 T10 T11
Interface Signal Active Signal
Hi-Z Hi-Z
( Input Data )
< Table 8. Sequence Table >
Values
Parameter Units
Min Typ Max
T1 0.5 - 10 ms
T2 0 - 50 ms
T3 200 - - ms
T10 200 - - ms
T11 0 - 50 ms
T12 1 - - s
Notes: 1. Even though T1 is over the specified value, there is no problem if I2T spec of fuse is satisfied.
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6.0 OPTICAL SPECIFICATIONS
The test of optical specifications shall be measured in a dark room (ambient luminance1 lux
and temperature=25