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LD420EUP
Product Specification
SPECIFICATION
FOR
APPROVAL
( ) Preliminary Specification
( ) Final Specification
Title 42.0" WUXGA TFT LCD
BUYER General SUPPLIER LG DISPLAY Co., Ltd.
MODEL *MODEL LD420EUP
SUFFIX SEA2
SIGNATURE SIGNATURE
APPROVED BY APPROVED BY
DATE DATE
K. S. Nah
/ / Chief Senior Engineer
REVIEWED BY
M.J. Lee
/ / Chief Senior Engineer
PREPARED BY
J.H. Song
/ / Senior Engineer
Please return 1 copy for your confirmation with PD Product Design Dept.
your signature and comments. LG Display Co., Ltd
Ver. 1.0 1 / 40
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LD420EUP
Product Specification
CONTENTS
Number ITEM Page
COVER 1
CONTENTS 2
RECORD OF REVISIONS 3
1 GENERAL DESCRIPTION 4
2 ABSOLUTE MAXIMUM RATINGS 5
3 ELECTRICAL SPECIFICATIONS 6
3-1 ELECTRICAL CHARACTERISTICS 6
3-2 INTERFACE CONNECTIONS 8
3-3 SIGNAL TIMING SPECIFICATIONS 11
3-4 LVDS SIGNAL SPECIFICATIONS 12
3-5 COLOR DATA REFERENCE 15
3-6 POWER SEQUENCE 16
4 OPTICAL SPECIFICATIONS 18
5 MECHANICAL CHARACTERISTICS 22
6 RELIABILITY 25
7 INTERNATIONAL STANDARDS 26
7-1 SAFETY 26
7-2 EMC 26
7-3 ENVIRONMENT 26
8 PACKING 27
8-1 INFORMATION OF LCM LABEL 27
8-2 PACKING FORM 27
9 PRECAUTIONS 28
9-1 MOUNTING PRECAUTIONS 28
9-2 OPERATING PRECAUTIONS 28
9-3 ELECTROSTATIC DISCHARGE CONTROL 29
9-4 PRECAUTIONS FOR STRONG LIGHT EXPOSURE 29
9-5 STORAGE 29
9-6 HANDLING PRECAUTIONS FOR PROTECTION FILM 29
9-7 APPROPRIATE CONDITION FOR PUBLIC DISPLAY 29
Ver. 1.0 2 / 40
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LD420EUP
Product Specification
RECORD OF REVISIONS
Revision No. Revision Date Page Description
1.0 Aug.14.2012 - Final Specification
Ver. 1.0 3 / 40
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LD420EUP
Product Specification
The LD420EUP is a Color Active Matrix Liquid Crystal Display with an integral Light Emitting Diode (LED)
b ac k l i g ht s ys t em . T he m a t r i x em p l o ys a - S i T h i n F i lm T r an s is t or a s t he a c t i v e e l em en t .
It is a transmissive display type which is operating in the normally black mode. It has a 42.02 inch diagonally
measured active display area with WUXGA resolution (1080 vertical by 1920 horizontal pixel array).
Each pixel is divided into Red, Green and Blue sub-pixels or dots which are arrayed in vertical stripes.
Gray scale or the luminance of the sub-pixel color is determined with a 10-bit gray scale signal for each dot.
Therefore, it can present a palette of more than 1.06Bilion colors. It has been designed to apply the 10-bit 4-port
LVDS interface. It is intended to support Public Display where high brightness, super wide viewing angle, high
color gamut, high color depth and fast response time are important.
EPI (RGB)
CN2 EEPROM
LVDS (41pin) Source Driver Circuit
2Port
LVDS 3,4 SCL SDA S1 S1920
LVDS G1
2Port LVDS 1,2
Timing Controller
LVDS Option LVDS Rx + L/D + DGA + ODC
Select signal Control
L-DIM
CN1 I2C
Integrated
Signals TFT - LCD Panel
Enable (51pin) (1920 RGB 1080 pixels)
Bit
Select
+12.0V Power Circuit Power Signals G1080
Block
1B 7B
SIN, SCLK, V_Sync
L-Dimming : 12 Block
+24.0V, GND, On/Off LED Driver
ExtVBR-B 6B 12B
General Features
Active Screen Size 42.02 inches(1067.31mm) diagonal
Outline Dimension 958.4(H) 551.3(V) X 10.8(B)/24.0 mm(D) (Typ.)
Pixel Pitch 0.4845 mm x 0.4845 mm
Pixel Format 1920 horiz. by 1080 vert. Pixels, RGB stripe arrangement
Color Depth 10bit(D), 1.06Billon colors
Luminance, White 700 cd/m2 (Center 1point ,Typ.)
Viewing Angle (CR>10) Viewing angle free ( R/L 178 (Min.), U/D 178 (Min.))
Power Consumption Total 91.5W(Typ.) [Logic= 8.3W, LED Driver=83.2W(ExtVbr_B=100% )]
Weight 9.2 Kg (Typ.)
Display Mode Transmissive mode, Normally black
Surface Treatment Hard coating(3H), Anti-glare treatment of the front polarizer (Haze 10%)
Possible Display Type Landscape and Portrait Enabled
Ver. 1.0 4 / 40
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LD420EUP
Product Specification
2. Absolute Maximum Ratings
The following items are maximum values which, if exceeded, may cause faulty operation or permanent damage
to the LCD module.
Table 1. ABSOLUTE MAXIMUM RATINGS
Value
Parameter Symbol Unit Note
Min Max
LCD Circuit VLCD -0.3 +14.0 VDC
Power Input Voltage
Driver VBL -0.3 + 27.0 VDC
ON/OFF VOFF / VON -0.3 +5.5 VDC 1
Driver Control Voltage
Brightness EXTVBR-B 0.0 +5.5 VDC
T-Con Option Selection Voltage VLOGIC -0.3 +4.0 VDC
Operating Temperature TOP 0 +50 C
2,3
Storage Temperature TST -20 +60 C
Panel Front Temperature TSUR - +68 C 4
Operating Ambient Humidity HOP 10 90 %RH
2,3
Storage Humidity HST 10 90 %RH
Note 1. Ambient temperature condition (Ta = 25 r 2 C )
2. Temperature and relative humidity range are shown in the figure below.
Wet bulb temperature should be Max 39 C, and no condensation of water.
3. Gravity mura can be guaranteed below 50 C condition.
4. The maximum operating temperatures is based on the test condition that the surface temperature
of display area is less than or equal to 68 C with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 68 . The range of operating temperature may be degraded in case of
improper thermal management in final product design. 90%
60
60%
50 Storage
Humidity [(%)RH]
Wet Bulb
Temperature [ C]
40
40%
Operation
30
20
10
0
10%
-20 0 10 20 30 40 50 60 70 80
Dry Bulb Temperature [ C]
Ver. 1.0 5 / 40
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LD420EUP
Product Specification
3. Electrical Specifications
3-1. Electrical Characteristics
It requires two power inputs. One is employed to power for the LCD circuit. The other Is used for the LED
backlight and LED Driver circuit.
Table 2. ELECTRICAL CHARACTERISTICS
Value
Parameter Symbol Unit Note
Min Typ Max
Circuit :
Power Input Voltage VLCD 10.8 12.0 13.2 VDC
- 690 900 mA 1
Power Input Current ILCD
- 975 1,265 mA 2
Power Consumption PLCD 8.3 10.8 Watt 1
Rush current IRUSH - - 3.0 A 3
Note
1. The specified current and power consumption are under the VLCD=12.0V, Ta=25 r 2 C, fV=120Hz condition,
and mosaic pattern(8 x 6) is displayed and fV is the frame frequency.
2. The current is specified at the maximum current pattern.
3. The duration of rush current is about 2ms and rising time of power input is 0.5ms (min.).
4. Ripple voltage level is recommended under 5% of typical voltage
White : 1023 Gray
Black : 0 Gray
Mosaic Pattern(8 x 6)
Ver. 1.0 6 / 40
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LD420EUP
Product Specification
Table 3. ELECTRICAL CHARACTERISTICS (Continue)
Values
Parameter Symbol Unit Notes
Min Typ Max
LED Driver :
Power Supply Input Voltage VBL 22.8 24.0 25.2 Vdc 1
Power Supply Input Current IBL - 3.46 3.73 A 1
VBL = 22.8V
Power Supply Input Current (In-Rush) In-rush - - 5.0 A Ext VBR-B = 100%
4
Power Consumption PBL - 83.2 89.5 W 1
On V on 2.5 - 5.0 Vdc
On/Off
Off V off -0.3 0.0 0.7 Vdc
On Duty
Brightness Adjust Ext VBR-B 1 - 100 %
Input Voltage for 6
Control System PAL 100 Hz 3
Signals PWM Frequency for
NTSC & PAL NTSC 120 Hz 3
Pulse Duty Level High Level 2.4 - 5.0 Vdc HIGH : on duty
(PWM) Low Level 0.0 - 0.7 LOW : off duty
Vdc
Life Time 50,000 60,000 Hrs 2
Notes :
1. Electrical characteristics are determined after the unit has been `ON' and stable for approximately 60
minutes at 25 2 C. The specified current and power consumption are under the typical supply Input voltage
24Vand VBR (ExtVBR-B : 100%), it is total power consumption.
2. The life time is determined as the time which luminance of the LED is 50% compared to that of initial
value at the typical LED current (ExtVBR-B :100%) on condition of continuous operating in LCM state at
25 2 C. (Min @ L50B10)
3. LGD recommend that the PWM freq. is synchronized with One time harmonic of V_sync signal of system.
Though PWM frequency is over 120Hz (max 252Hz), function of LED Driver is not affected.
4. The duration of rush current is about 200ms. This duration is applied to LED on time.
5. Even though inrush current is over the specified value, there is no problem if I2T spec of fuse is satisfied.
6. Ext_PWM Signal have to input available duty range.
Between 99% and 100% ExtVBR-B duty have to be avoided. ( 99% < ExtVBR-B < 100%)
But ExtVBR-B 0% and 100% are available.
High
Available duty range
Low
0% 1% Ext_PWM Input Duty 99% 100%
Ver. 1.0 7 / 40
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LD420EUP
Product Specification
3-2. Interface Connections
This LCD module employs two kinds of interface connection, 51-pin connector and 41-pin connector are used
for the module electronics and 14-pin connector is used for the integral backlight system.
3-2-1. LCD Module
- LCD Connector(CN1): FI-RE51S-HF(manufactured by JAE) or compatible
- Mating Connector : FI-R51HL(JAE) or compatible
Table 4-1. MODULE CONNECTOR(CN1) PIN CONFIGURATION
No Symbol Description No Symbol Description
1 NC Note 4 27 Bit Select H or NC= 10bit(D) , L = 8bit
2 NC Note 4 28 R2AN SECOND LVDS Receiver Signal (A-)
3 NC Note 4 29 R2AP SECOND LVDS Receiver Signal (A+)
4 NC Note 4 30 R2BN SECOND LVDS Receiver Signal (B-)
5 NC Note 4 31 R2BP SECOND LVDS Receiver Signal (B+)
6 NC Note 4 32 R2CN SECOND LVDS Receiver Signal (C-)
7 LVDS Select H =JEIDA , L or NC = VESA 33 R2CP SECOND LVDS Receiver Signal (C+)
8 NC Note 4 34 GND Ground
9 NC Note 4 35 R2CLKN SECOND LVDS Receiver Clock Signal(-)
10 L-DIM Enable H Only, Note 5 36 R2CLKP SECOND LVDS Receiver Clock Signal(+)
11 GND Ground 37 GND Ground
12 R1AN FIRST LVDS Receiver Signal (A-) 38 R2DN SECOND LVDS Receiver Signal (D-)
13 R1AP FIRST LVDS Receiver Signal (A+) 39 R2DP SECOND LVDS Receiver Signal (D+)
14 R1BN FIRST LVDS Receiver Signal (B-) 40 R2EN SECOND LVDS Receiver Signal (E-)
15 R1BP FIRST LVDS Receiver Signal (B+) 41 R2EP SECOND LVDS Receiver Signal (E+)
16 R1CN FIRST LVDS Receiver Signal (C-) 42 NC or GND No Connection or Ground
17 R1CP FIRST LVDS Receiver Signal (C+) 43 NC or GND No Connection or Ground
18 GND Ground 44 GND Ground
19 R1CLKN FIRST LVDS Receiver Clock Signal(-) 45 GND Ground
20 R1CLKP FIRST LVDS Receiver Clock Signal(+) 46 GND Ground
21 GND Ground 47 NC No connection
22 R1DN FIRST LVDS Receiver Signal (D-) 48 VLCD Power Supply +12.0V
23 R1DP FIRST LVDS Receiver Signal (D+) 49 VLCD Power Supply +12.0V
24 R1EN FIRST LVDS Receiver Signal (E-) 50 VLCD Power Supply +12.0V
25 R1EP FIRST LVDS Receiver Signal (E+) 51 VLCD Power Supply +12.0V
26 NC or GND NC or Ground - - -
Note:
1. All GND (ground) pins should be connected together to the LCD module's metal frame.
2. All VLCD (power input) pins should be connected together.
3. All input levels of LVDS signals are based on the EIA 644 Standard.
4. These pins are reserved only for LGD (Do not connect)
5. All evaluation was verified based on L-DIM "H" and should keep "H" status during the operation.
Ver. 1.0 8 / 40
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LD420EUP
Product Specification
-LCD Connector (CN2) : FI-RE41S-HF (manufactured by JAE) or compatible
- Mating Connector : FI-RE41HL
Table 4-2. MODULE CONNECTOR(CN2) PIN CONFIGURATION
No Symbol Description No Symbol Description
1 NC No connection 22 RE3N THIRD LVDS Receiver Signal (E-)
2 NC No connection 23 RE3P THIRD LVDS Receiver Signal (E+)
3 NC No connection 24 GND Ground
4 NC No connection 25 GND Ground
5 NC No connection 26 RA4N FORTH LVDS Receiver Signal (A-)
6 NC No connection 27 RA4P FORTH LVDS Receiver Signal (A+)
7 NC No connection 28 RB4N FORTH LVDS Receiver Signal (B-)
8 NC No connection 29 RB4P FORTH LVDS Receiver Signal (B+)
9 GND Ground 30 RC4N FORTH LVDS Receiver Signal (C-)
10 RA3N THIRD LVDS Receiver Signal (A-) 31 RC4P FORTH LVDS Receiver Signal (C+)
11 RA3P THIRD LVDS Receiver Signal (A+) 32 GND Ground
12 RB3N THIRD LVDS Receiver Signal (B-) 33 RCLK4N FORTH LVDS Receiver Clock Signal(-)
13 RB3P THIRD LVDS Receiver Signal (B+) 34 RCLK4P FORTH LVDS Receiver Clock Signal(+)
14 RC3N THIRD LVDS Receiver Signal (C-) 35 GND Ground
15 RC3P THIRD LVDS Receiver Signal (C+) 36 RD4N FORTH LVDS Receiver Signal (D-)
16 GND Ground 37 RD4P FORTH LVDS Receiver Signal (D+)
17 RCLK3N THIRD LVDS Receiver Clock Signal(-) 38 RE4N FORTH LVDS Receiver Signal (E-)
18 RCLK3P THIRD LVDS Receiver Clock Signal(+) 39 RE4P FORTH LVDS Receiver Signal (E+)
19 GND Ground 40 GND Ground
20 RD3N THIRD LVDS Receiver Signal (D-) 41 GND Ground
21 RD3P THIRD LVDS Receiver Signal (D+) -
Note :
1. All GND (ground) pins should be connected together to the LCD module's metal frame.
2. LVDS pin (pin No. #22,23,38,39) are used for 10Bit(D) of the LCD module.
If used for 8Bit(R), these pins are no connection.
#1
CN3 #10 CN1 CN2
#1 #51 #1 #41
CN3 #10 #1
CN1 #51 #1
CN2 #41
#1
Rear view of LCM
Ver. 1.0 9 / 40
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LD420EUP
Product Specification
3-2-2. Backlight Module
Master
-LED Driver Connector
: 20022WR - H14B2(Yeonho)
Mating Connector
: 20022HS - 14B2(Yeonho)
Table 5. LED DRIVER CONNECTOR PIN CONFIGURATION
Pin No Symbol Description Note
1 VBL Power Supply +24.0V
2 VBL Power Supply +24.0V
3 VBL Power Supply +24.0V
4 VBL Power Supply +24.0V
5 VBL Power Supply +24.0V
6 GND Backlight Ground
7 GND Backlight Ground
8 GND Backlight Ground 1
9 GND Backlight Ground
10 GND Backlight Ground
11 Status Back Light Status 2
12 VON/OFF Backlight ON/OFF control
13 NC Don't care
14 EXT VBR-B External PWM 3
Notes :1. GND should be connected to the LCD module's metal frame.
2. Normal : Low (under 0.7V) / Abnormal : Open
3. High : on duty / Low : off duty, Pin#14 can be opened. ( if Pin #14 is open , EXT VBR-B is 100% )
4. Each impedance of pin #12 and 14 is over 50 [K] .
Rear view of LCM Status
PCB
1 14
1 14
...
...
Ver. 1.0 10 / 40
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LD420EUP
Product Specification
3-3. Signal Timing Specifications
Table 6 shows the signal timing required at the input of the LVDS transmitter. All of the interface signal
timings should be satisfied with the following specification for normal operation.
Table 6. TIMING TABLE (DE Only Mode)
ITEM Symbol Min Typ Max Unit Note
Display
tHV 480 480 480 tCLK 1920 / 4
Period
Horizontal
Blank tHB 40 70 200 tCLK 1
Total tHP 520 550 680 tCLK
Display
tVV 1080 1080 1080 Lines
Period
20 45 86
Vertical Blank tVB Lines 1
(228) (270) (300)
1100 1125 1166
Total tVP Lines
(1308) (1350) (1380)
ITEM Symbol Min Typ Max Unit Note
DCLK fCLK 66.97 74.25 78.00 MHz
Horizontal fH 121.8 135 140 KHz 2
Frequency
2
108 120 122
Vertical fV Hz NTSC
(95) (100) (104)
(PAL)
Note:
1. The input of HSYNC & VSYNC signal does not have an effect on normal operation (DE Only Mode).
If you use spread spectrum of EMI, add some additional clock to minimum value for clock margin.
2. The performance of the electro-optical characteristics may be influenced by variance of the vertical
refresh rate and the horizontal frequency
Timing should be set based on clock frequency.
Ver. 1.0 11 / 40
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Product Specification
3-4. LVDS Signal Specification
3-4-1. LVDS Input Signal Timing Diagram
0.7VDD
DE, Data
0.3VDD
tCLK
DCLK 0.5 VDD
Valid data
First data Invalid data Pixel 0 Pixel 4 Invalid data
Valid data
Second data Invalid data Pixel 1 Pixel 5 Invalid data
Valid data
Third data Invalid data Pixel 2 Pixel 6 Invalid data
Valid data
Forth data Invalid data Pixel 3 Pixel 7 Invalid data
DE(Data Enable)
* tHB = tHFP + tWH +tHBP
* tVB = tVFP + tWV +tVBP
1 1080
DE(Data Enable)
tVV
tVP
Ver. 1.0 12 / 40
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Product Specification
3-4-2. LVDS Input Signal Characteristics
1) DC Specification
LVDS -
LVDS +
V CM V IN _ MAX V IN _ MIN
# V CM = {( LVDS +) + ( LVDS - )} /2
0V
Description Symbol Min Max Unit Note
LVDS Common mode Voltage VCM 1.0 1.5 V -
LVDS Input Voltage Range VIN 0.7 1.8 V -
Change in common mode Voltage VCM - 250 mV -
2) AC Specification
T clk
LVDS Clock
A
LVDS Data
( F clk = 1 /T clk )
tSKEW tSKEW
A
Tclk
LVDS 1'st Clock 80%
LVDS 2nd / 3rd / 4th Clock
20%
tRF
tSKEW_min tSKEW_max
Description Symbol Min Max Unit Note
High Threshold VTH 100 600 mV
LVDS Differential Voltage 3
Low Threshold VTL -600 -100 mV
LVDS Clock to Data Skew tSKEW - |(0.25*Tclk)/7| ps -
LVDS Clock/DATA Rising/Falling time tRF 260 |(0.3*Tclk)/7| ps 2
Effective time of LVDS teff | 360| - ps -
LVDS Clock to Clock Skew (Even to Odd) tSKEW_EO - |1/7* Tclk| ps -
Note 1. All Input levels of LVDS signals are based on the EIA 644 Standard.
2. If tRF isn't enough, teff should be meet the range.
3. LVDS Differential Voltage is defined within teff
Ver. 1.0 13 / 40
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Product Specification
0.5tui tui
LVDS Data
360ps
VTH
0V
(Differential) VTL
360ps
teff
LVDS CLK tui : Unit Interval
0V
(Differential)
* This accumulated waveform is tested with differential probe
Ver. 1.0 14 / 40
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Product Specification
3-5. Color Data Reference
The brightness of each primary color (red, green, blue) is based on the 10bit gray scale data input for the color.
The higher binary input, the brighter the color. Table 7 provides a reference for color versus data input.
Table 7. COLOR DATA REFERENCE
Input Color Data
RED GREEN BLUE
Color
MSB LSB MSB LSB MSB LSB
Black
Red (1023)
Green (1023)
Basic Blue (1023)
Color Cyan
Magenta
Yellow
White
RED (0000)
RED (0001)
RED ...
RED (1022)
RED (1023)
GREEN (0000)
GREEN (0001)
GREEN ...
GREEN (1022)
GREEN (1023)
BLUE (0000)
BLUE (0001)
BLUE ...
BLUE (1022)
BLUE (1023)
Ver. 1.0 15 / 40
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Product Specification
3-6. Power Sequence
3-6-1. LCD Driving circuit
90% 90%
Power Supply For LCD
VLCD 10% 10% 10%
0V
T8
T1
T5
T2
Valid Data Vcm : LVDS Common mode Voltage
30%
Interface Signal (Tx_clock) 0V
100% T3 T4
T6
User Control Signal
(LVDS_SEL, BIT_SEL, L-DIM EN)
Power for LED T7 LED ON
Table 8. POWER SEQUENCE
Value
Parameter Unit notes
Min Typ Max
T1 0.5 - 20 ms 1
T2 0 - - ms 2
T3 200 - - ms 3
T4 200 - - ms 3
T5 1.0 - - s 4
T6 - - T2 ms 5
T7 0.5 - - s 6
T8 100 - - ms 7
notes : 1. Even though T1 is over the specified value, there is no problem if I2T spec of fuse is satisfied.
2. If T2 is satisfied with specification after removing LVDS Cable, there is no problem.
3. The T3 / T4 is recommended value, the case when failed to meet a minimum specification,
abnormal display would be shown. There is no reliability problem.
4. T5 should be measured after the Module has been fully discharged between power off and on period.
5. If the on time of signals (Interface signal and user control signals) precedes the on time of Power (VLCD),
it will be happened abnormal display. When T6 is NC status, T6 doesn't need to be measured.
6. If there is no abnormal display, no problem.
7. It is recommendation specification that T8 has to be 100ms as a minimum value.
Please avoid floating state of interface signal at invalid period.
When the power supply for LCD (VLCD) is off, be sure to pull down the valid and invalid data to 0V.
Ver. 1.0 16 / 40
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Product Specification
3-6-2. Sequence for LED Driver
Power Supply For LED Driver
24V (typ.)
90% 90%
VBL
10%
0V
T1 T2 T3
VON/OFF
LED ON
T4
Ext-VBR-B
3-6-3. Dip condition for LED Driver
T5
VBL : 24V
VBL(Typ.) x 0.8
0V
Table 9. Power Sequence for LED Driver
Values
Parameter Units Remarks
Min Typ Max
T1 20 - - ms 1
T2 500 - - ms
T3 10 - ms
T4 0 - - ms
T5 - - 10 ms VBL(Typ) x 0.8
Notes :
1. T1 describes rising time of 0V to 24V and this parameter does not applied at restarting time.
Even though T1 is over the specified value, there is no problem if I2T spec of fuse is satisfied.
Ver. 1.0 17 / 40
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Product Specification
4. Optical Specification
Optical characteristics are determined after the unit has been `ON' and stable in a dark environment at 25 2 C.
The values are specified at distance 50cm from the LCD surface at a viewing angle of ) and T equal to 0 .
FIG. 1 shows additional information concerning the measurement equipment and method.
LCD Module Pritchard 880 or
Optical Stage(x,y)
equivalent
50cm
FIG. 1 Optical Characteristic Measurement Equipment and Method
Ta= 25 2 C, VLCD=12.0V, fV=120Hz, Dclk=74.25MHz,
Table 10. OPTICAL CHARACTERISTICS EXTVBR-B =100%
Value
Parameter Symbol Unit Note
Min Typ Max
Contrast Ratio CR 1,100 1,300 - 1
Surface Luminance, white LWH 560 700 - cd/m2 2
Luminance Variation G WHITE 5P - - 1.3 3
Response Time
Gray-to-Gray G to G - 12 15 ms 4,5
Rx 0.641
RED
Ry 0.334
Gx 0.301
GREEN
Color Coordinates Gy Typ 0.615 Typ
[CIE1931] Bx -0.03 0.154 +0.03
BLUE
By 0.058
Wx 0.279
WHITE
Wy 0.292
Color Temperature 10,000 K
Color Gamut 72 %
Viewing Angle (CR>10)
x axis, right(I=0 ) Tr 89 - -
x axis, left (I=180 ) Tl 89 - -
degree 5
y axis, up (I=90 ) Tu 89 - -
y axis, down (I=270 ) Td 89 - -
Gray Scale - - - 6
Ver. 1.0 18 / 40
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LD420EUP
Product Specification
Note : 1. Contrast Ratio(CR) is defined mathematically as :
Surface Luminance with all white pixels
Contrast Ratio =
Surface Luminance with all black pixels
It is measured at center 1-point.
2. Surface luminance is determined after the unit has been `ON' and 1 Hour after lighting the
backlight in a dark environment at 25 2 C. Surface luminance is the luminance value at center
1-point across the LCD surface 50cm from the surface with all pixels displaying white.
For more information see the FIG. 2.
3. The variation in surface luminance , G WHITE is defined as :
G WHITE(5P) = Maximum(Lon1,Lon2, Lon3, Lon4, Lon5) / Minimum(Lon1,Lon2, Lon3, Lon4, Lon5)
Where Lon1 to Lon5 are the luminance with all pixels displaying white at 5 locations .
For more information, see the FIG. 2.
4. Response time is the time required for the display to transit from G(N) to G(M) (Rise Time, Tr R)
and from G(M) to G(N) (Decay Time, Tr D). For additional information see the FIG. 3. (N
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