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Panel_SHARP_LQ150X1LG55_0_[DS]


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   Global LCD Panel Exchange Center           www.panelook.com




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                                      RECORDS OF REVISION
          LQ150X1LG55
           SPEC No.        DATE       REVISED                       SUMMARY                  NOTE
                                        No.     PAGE
          LD-19512A     May.18.2007      -       -                     -                  1 st Issue




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                                                                                                                LD19512A-1
         1. Application
               This specification applies to the color 15.0 XGA TFT-LCD module LQ150X1LG55.


           These specification sheets are the proprietary product of SHARP CORPORATION("SHARP) and include
           materials protected under copyright of SHARP. Do not reproduce or cause any third party to reproduce them in
           any form or by any means, electronic or mechanical, for any purpose, in whole or in part, without the express
           written permission of SHARP.


           The device listed in these specification sheets was designed and manufactured for use in general electronic
           equipment.


           In case of using the device for applications such as control and safety equipment for transportation (controls of
           aircraft, trains, automobiles, etc.), rescue and security equipment and various safety related equipment which
           require higher reliability and safety, take into consideration that appropriate measures such as fail-safe
           functions and redundant system design should be taken.


           Do not use the device for equipment that requires an extreme level of reliability, such as aerospace applications,
           telecommunication equipment(trunk lines), nuclear power control equipment and medical or other equipment
           for life support.


           SHARP assumes no responsibility for any damage resulting from the use of the device which does not comply
           with the instructions and the precautions specified in these specification sheets.


           Confirm "11. Handling Precautions " item when you use the device.


           Contact and consult with a SHARP sales representative for any questions about this device.




         2. Overview
          This module is a color active matrix LCD module incorporating amorphous silicon TFT         (Thin Film Transistor).
         It is composed of a color TFT-LCD panel, driver ICs, control circuit, power supply circuit and a back light unit.
         Graphics and texts can be displayed on a 1024      RGB     768 dots panel with about 16 million colors by using
         LVDS (Low Voltage Differential Signaling) and supplying +3.3V DC supply voltages for TFT-LCD panel
         driving and supply voltage for backlight. Backlight-driving DC/AC inverter is not built in this module.
         This TFT-LCD module conforms to PSWG. Viewing angle is 6 o'clock direction.




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                                                                                                    LD19512A-2
         3. Mechanical Specifications
                                  Parameter                         Specifications          Unit
                         Display size                      38 (Diagonal)                     cm
                                                           15.0 (Diagonal)                  Inch
                         Active area                       304.1 (H) 228.1 (V)              mm
                         Pixel format                      1024 (H) 768 (V)                 Pixel
                                                           (1 pixel R+G+B dots)
                         Pixel pitch                       0.297 (H) 0.297 (V)              mm
                         Pixel configuration               R, G, B vertical stripe
                         Display mode                      Normally white
                         Unit outline dimensions *1        326.5(W) 253.5(H) 11.2(D)        mm
                         Mass                              1000 (Max)                        g
                         Surface treatment                 Anti-glare and hard-coating 3H
                                                           (Haze value = 25)
                  *1.Note: excluding back light cables, cover and pet sheet.
                     The thickness of module (D) doesn't contain the projection.
                     Outline dimensions are shown in Fig.1.




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                                                                                                              LD19512A-3
         4. Input Terminals
          4-1. TFT-LCD panel driving
           CN1 (Interface signals and +3.3V DC power supply)
             Using connectors                      DF14H-20P-1.25H (Hirose Electric Co., Ltd.)
             Corresponding connectors              DF14-20S-1.25C(Hirose Electric Co., Ltd.)


                                                                 Please do not use it besides corresponding conector
            Pin No.     Symbol                                 Function                              Remark
               1          Vcc           +3.3V Power supply
               2          Vcc           +3.3V Power supply
               3          GND
               4          GND
               5        RXIN0-          Receiver signal (-)                                           LVDS
               6        RXIN0+          Receiver signal (+)                                           LVDS
               7          GND
               8        RXIN1-          Receiver signal (-)                                           LVDS
               9        RXIN1+          Receiver signal (+)                                           LVDS
               10         GND
               11       RXIN2-          Receiver signal (-)                                           LVDS
               12       RXIN2+          Receiver signal (+)                                           LVDS
               13         GND
               14      RXCKIN-          Clock signal (-)                                              LVDS
               15      RXCKIN+          Clock signal (+)                                              LVDS
               16         GND
               17       RXIN3-          Receiver signal (-)                                           LVDS
               18       RXIN3+          Receiver signal (+)                                           LVDS
               19      HANTEN           Horizontal/Vertical display mode select signal                note2
               20     LVDS_SET          LVDS_SET                                                      note1


             note2




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                                                                                          LD19512A-4
          4-2. Data Mapping
          1) 8 bit input
              note1 pin assignment with LVDS_SET pin (Thine: THC63LVDF83A)


                           Transmitter                20pin LVDS_SET
                    Pin No          Data      = H (3.3V)        = L (GND) or Open
                      51            TA0          R2                 R0 (LSB)
                      52            TA1          R3                    R1
                      54            TA2          R4                    R2
                      55            TA3          R5                    R3
                      56            TA4          R6                    R4
                       3            TA5      R7 (MSB)                  R5
                       4            TA6          G2                 G0 (LSB)
                       6            TB0          G3                    G1
                       7            TB1          G4                    G2
                      11            TB2          G5                    G3
                      12            TB3          G6                    G4
                      14            TB4      G7 (MSB)                  G5
                      15            TB5          B2                 B0 (LSB)
                      19            TB6          B3                    B1
                      20            TC0          B4                    B2
                      22            TC1          B5                    B3
                      23            TC2          B6                    B4
                      24            TC3      B7 (MSB)                  B5
                      27            TC4      High or low           High or low
                      28            TC5      High or low           High or low
                      30            TC6          DE                    DE
                      50            TD0       R0 (LSB)                 R6
                       2            TD1          R1                R7 (MSB)
                       8            TD2       G0 (LSB)                 G6
                      10            TD3          G1                G7 (MSB)
                      16            TD4       B0 (LSB)                 B6
                      18            TD5          B1                B7 (MSB)
                      25            TD6         (NA)                  (NA)
                      31           CLK IN       CLK                   CLK




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                                                                                            LD19512A-5
         
                                                                 1 cycle

             RXCKIN+
             RXCKIN-



              RXIN0+
                                   R3   R2   G2       R7    R6       R5     R4   R3   R2      G2
              RXIN0-


              RXIN1+
                                   G4   G3   B3       B2    G7       G6     G5   G4   G3      B3
              RXIN1-


              RXIN2+
                                   B5   B4   DE       NA    NA       B7     B6   B5   B4      DE
              RXIN2-

              RXIN3+
                                   R1   R0   NA       B1    B0       G1     G0   R1   R0      NA
              RXIN3-

             DE : Display Enable
             NA : Not Available


         


                                                                  1 cycle


             RXCXIN+

             RXCXIN-




              RXIN0+
                                   R1   R0   G0       R5    R4       R3     R2   R1    R0      G0
              RXIN0-


              RXIN1+
                                   G2   G1   B1       B0    G5       G4     G3   G2    G1      B1
              RXIN1-



              RXIN2+
                                   B3   B2   DE       NA    NA       B5     B4   B3    B2      DE
              RXIN2-

              RXIN3+
                                   R7   R6   NA       B7    B6       G7     G6   R7    R6      NA
              RXIN3-

             DE : Display Enable
             NA : Not Available




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                                                                                                     LD19512A-6
          2) 6 bit input
              note1 pin assignment with LVDS_SET pin (Thine: THC63LVDF83A)
                           Transmitter                            20pin LVDS_SET
                   Pin No              Data             = H (3.3V)         = L (GND) or Open
                      51            TA0                  R0 (LSB)
                      52            TA1                     R1
                      54            TA2                     R2
                      55            TA3                     R3
                      56            TA4                     R4
                       3            TA5                 R5 (MSB)
                       4            TA6                  G0 (LSB)
                       6            TB0                     G1
                       7            TB1                     G2
                      11            TB2                     G3
                      12            TB3                     G4
                      14            TB4                 G5 (MSB)
                      15            TB5                  B0 (LSB)
                      19            TB6                     B1
                      20            TC0                     B2
                      22            TC1                     B3
                      23            TC2                     B4
                      24            TC3                 B5 (MSB)
                      27            TC4                 High or low
                      28            TC5                 High or low
                      30            TC6                     DE
                      50            TD0                    GND
                       2            TD1                    GND
                       8            TD2                    GND
                      10            TD3                    GND
                      16            TD4                    GND
                      18            TD5                    GND
                      25            TD6                    (NA)
                      31           ClKIN                   CLK

                                         1 cycle

         RXCKIN+
         RXCKIN-



          RXIN0+
                                  R1          R0   G0        R5       R4   R3      R2    R1    R0   G0
          RXIN0-


          RXIN1+
                                  G2          G1   B1        B0       G5   G4      G3    G2    G1   B1
          RXIN1-


          RXIN2+
                                  B3          B2   DE        NA       NA   B5      B4    B3    B2   DE
          RXIN2-

          DE : Display Enable
          NA : Not Available
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    4-3 Interface block diagram                                                                                                            LD-19512A-7

                          (Computer Side)                                                                                 (TFT-LCD side)
      8Bit Mode
    LVDS_SET=L (20 pin=GND or OPEN)


            Controller                   THC63LVDM83R                                   Single LVDS interface contained in a control
                          7                                                RXIN0+(6)                          RA 0 - 6
             R0-R5,G0         TA 0 - 6
                          7                                                RXIN0-(5)                                           RB 0 - 6




                                              TTL PARALLEL-TO-LVDS




                                                                                                   LVDS-TO-PARALLEL TTL
           G1-G5,B0,B1        TB 0 - 6
                          7   TC 0 - 6                                     RXIN1+(9)                                           RC 0 - 6
       B2-B5, NA,NA,DE
                          7   TD 0 - 6                                     RXIN1-(8)                                           RD 0 - 6




                                                                                                                                                Internal circuits
           R6,R7,G6,G7,
            B6,B7,NA                                                       RXIN2+(12)
                                                                           RXIN2-(11)

                                                                           RXIN3+(18)
                                                                           RXIN3-(17)


                                                                         RXCKIN+(15)
                               C K IN                                                                                          CK OUT
                     CK                     PLL                          RX KIN-(14)            PLL




      8Bit Mode
    LVDS_SET=H (20 pin=3.3[V])


           Controller                    THC63LVDM83R
                                                                                        Single LVDS interface contained in a control IC
                          7                                                RXIN0+(6)                          RA 0 - 6
             R2-R7,G2         TA 0 - 6
                                                                           RXIN0-(5)
                          7                                                                        LVDS-TO-PARALLEL TTL
                                             TTL PARALLEL-TO-LVDS




                              TB 0 - 6                                                                                         RB 0 - 6
           G3-G7,B2,B3
                          7   TC 0 - 6                                     RXIN1+(9)                                           RC 0 - 6
       B4-B7, NA,NA,DE
                          7                                                RXIN1-(8)                                           RD 0 - 6
                              TD 0 - 6




                                                                                                                                               Internal circuits
           R0,R1,G0,G1,
            B0,B1,NA                                                       RXIN2+(12)
                                                                           RXIN2-(11)

                                                                           RXIN3+(18)
                                                                           RXIN3-(17)


                                                                          RXCKIN+(15)
                              C K IN                                                                                           CK OUT
                     CK                     PLL                           RX KIN-(14)           PLL




      6Bit Mode
    LVDS_SET=H (20 pin=3.3[V])


            Controller                   THC63LVDM83R
                                                                                        Single LVDS interface contained in a control IC
                          7                                                RXIN0+(6)                          RA 0 - 6
             R0-R5,G0         TA 0 - 6
                                                                           RXIN0-(5)
                                                                                                   LVDS-TO-PARALLEL TTL




                          7
                                              TTL PARALLEL-TO-LVDS




                              TB 0 - 6                                                                                         RB 0 - 6
           G1-G5,B0,B1
                          7   TC 0 - 6                                     RXIN1+(9)                                           RC 0 - 6
       B2-B5, NA,NA,DE
                          7                                                RXIN1-(8)                                           RD 0 - 6
                              TD 0 - 6
                                                                                                                                                Internal circuits




            ALL NA
                                                                           RXIN2+(12)
                                                                           RXIN2-(11)

                                                                           RXIN3+(18)
                                                                           RXIN3-(17)


                                                                          RXCKIN+(15)
                               C K IN                                                                                          CK OUT
                     CK                     PLL                           RX KIN-(14)           PLL




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                                                                                                                                                       LD19512A-8
          4-4. Backlight
          CN 2, 3
              The module-side connector                             BHR-03VS-1              (JST)
              The user-side connector                               SM02(8.0)B-BHS-1-TB(LF)(SN)                             (JST)
             Pin no.    symbol              I/O                                               Function                                                   Color
                1           HIGH              I            Power supply for lamp                (High voltage side)                                      Pink
                2          N.C.
                3           LOW               I            Power supply for lamp                (Low voltage side)                                       White


                                        1     Pink cable is VHIGH

                              CN2                                             Signal processing board
                                        3     White cable is VLOW                                                 CN1

                                                                                                             20         1


                                                                                                         Insert direction


                                                                                 TFT LCD back view
                                            White cable is VLOW
                                    3

                              CN3
                                    1 Pink cable is V
                                                      HIGH




         5. Absolute Maximum Ratings
                       Parameter                        Symbol            Condition                          Ratings                    Unit      Remark
             Supply voltage                                Vcc             Ta=25                        -0.3        + 4.0
             Input voltage(LVDS Signal)                    VI1             Ta=25                        -0.3            Vcc
             Input voltage(LVDS_SET)                       VI2             Ta=25                    -0.3           Vcc+ 0.3
             Storage temperature                          TSTG                                          -25         + 60                           Note1
             Operating temperature                        TOPA           Panel surface                   0         + 60
              Lamp Voltage                                VLa                                                  2000                      rms


           Note1    Humidity 95%RH Max.                           ( Ta   40      )
                                   Maximum wet-bulb temperature at 39                             or less. ( Ta>40                  )
                                   No condensation.


         6. Recommended operation condition
                  Parameter          Symbol                              Min.          Typ.              Max.                Unit          Remark

              Supply voltage                       Vcc                    3.0          +3.3                  3.6                               Note1
              LVDS Signals                         VL                     0                                2.4                                 Note2
              Input voltage                        VI                     0                                Vcc                                 Note3
              Surface temperature                  Topa                   0                                +60                                 Note4




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                                                                                                                              LD19512A-9
           Note1     On-off conditions for supply voltage
                    040 oC.
                       No condensation.


         7. Electrical Characteristics
          7-1. TFT-LCD panel driving                                                                      Ta    25
                        Parameter                      Symbol    Min.      Typ.    Max.     Unit                 Remark
             Vcc           Supply voltage              Vcc       +3.0      +3.3    +3.6          V
                           Current dissipation         Icc                 300      400      mA                   Note2
             Permissive input ripple voltage           VRF                         100     mVp-p           Vcc=+3.3V
             Differential input             High        VTH                        +100      mV            VCM=+1.2V
             Threshold voltage              Low         VTL      



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