Service Manuals, User Guides, Schematic Diagrams or docs for : . Various Wind Top AE1900 ms-6638 7438 rev 1.0
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1
COVER SHEET
BLOCK DIAGRAM
1
2
MS-7438 (MS-6638)
CLOCK MAP 3
Version 1.0
POWER MAP 4
CPU:
GPIO MAP 5
Intel Diamondville-CPU Intel Dimondville
6-7
VRM Single Phase 8
Intel Lakeport -GMCH 9-12
DDR II SO-DIMM 13-14 System Chipset:
Mini PCIE Slot 15 Intel 945GC (North Bridge)
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LAN 8111C 16 Intel ICH7(South Bridge)
VGA CONNECTOR 17
Clock Generator -RTM876-665-LF 18 On Board Chipset:
ICH7R 19-21
TPM LPC Debug port BIOS -- SPI
22
USB CONNECTORS HD AUDIO CODEC(ALC888)
23
HD AUDIO CODEC(ALC 888) 24 LAN -- Realtek RTL8111C
+19V DC-IN 25
Clock Generator -RTM876-665-LF
A A
5DUAL-PCIRST# 26 Main Memory:
F_ PANEL 27
Memory on board 1GB
SATA & CF_Card & FAN CONTROL 28
ACPI Controller OR
29
Auto BOM manual DDR II SO-DIMM x 1 (Max 2GB)
30
PWOK MAP 31
History 32
Super IO 33 Expansion Slots:
DDR2 64Mbx16 BGA A 34
Internal Mini PCIE x1
DDR2 64Mbx16 BGA B 35
LVDS INV 36 Intersil PWM:
MXM 37 Controller: 6314
Digitally signed by dd
DN: cn=dd, o=dd, ou=dd,
[email protected],
c=US MSI
MICRO-STAR INt'L CO., LTD.
Date: 2010.01.19 19:15:37
Title
COVER SHEET
+07'00'
Size Document Number Rev
MS-7438 1.0
Date: Friday, February 06, 2009 Sheet 1 of 36
1
1 2 3 4 5
A
VRM
1-Phase PWM
Intel Atom
>1.6GHz, DC /SC Block Diagram A
FSB
533
DDR II On Board 1G for SC
RGB
Analog Video OR
Pin Header Lakeport
945GC DDR II 533 SO-DIMM x1 DC
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SDVO
LVDS Scaler
DMI
B B
PCI Express x1 Mini PCIE1
SATA
SATA 0~1
ICH7
USB
USB Port 0~7 PCI Express x1
Realtek RTL8111C
include 1.Cardreader 2.WebCam GbE LAN
3.Touch Panel 4.MiniPCIE Slot
Azalia Codec SIO
C
ALC888 C
SPI
Modem
BIOS
D D
MICRO-START INT'L CO.,LTD.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3 MS-7438 1.0
Date: Friday, February 06, 2009 Sheet 2 of 36
1 2 3 4 5
5 4 3 2 1
HCLK Atom DC
CLOCK MAP P_DDR0_A
N_DDR0_A
266MHz
266MHz
DDRII
D MCHCLK P_DDR1_A 266MHz
SO-DIMM D
N_DDR1_A 266MHz
PE_100M Lakeport
DDRII
MCH On Board
DOTCLK
RTM876-665-LF
ICHCLK
SATACLK
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Clock 24MHz
USB48MHz ALC888 Azalia
Generator ICH7
ICH14.318MHz
32.768MHz
C C
48MHz
SIO
48MHz
4in1 CardReader
PE_100M
Mini PCIE
100MHz
B B
PE_100M LAN Realtek
100MHz 8111C
LPC Debug port
33MHz
A A
MSI MICRO-STAR INt'L CO., LTD.
Title
CLOCK MAP
Size Document Number Rev
1.0
MS-7438
Date: Friday, February 06, 2009 Sheet 3 of 36
5 4 3 2 1
5 4 3 2 1
POWER MAP
DC19V IN
PCIE1
D D
+12V +5V +3.3V +5VSB
8A
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VRM Diamondville
MSI
ACPI VCC_DDR
C
Logic gate
7.95*1.8/5/0.8 = 3.58A 6.75+1.2 = 7.95A
Lakeport C
VCC5_SB 4.4A
UPI MCH
0.9A
13.8A + 1.5A
V_1P5_CORE = 15.3A
VCC5 22.84A 17.08A
UPI 2.35A SO-DIMM
1.2A DDR2 X 1
V_1P05_CORE0.86A
LINEAR 1.78A
0.86A
0.86A 14mA
ICH7
V_FSB_VTT 0.375A
4.9A
B
4.9A
LINEAR B
0.375A
VCC3_SB VTT_DDR 1.2A
W83310DS
5VDUAL 3A
USB
A A
MSI MICRO-STAR INt'L CO., LTD.
Title
POWER MAP
Size Document Number Rev
1.0
MS-7438
Date: Friday, February 06, 2009 Sheet 4 of 36
5 4 3 2 1
8 7 6 5 4 3 2 1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name or status
GPIO[0] SIO_SMI# AB18 I/O Vcc3p3 N Y 5 Input pull high VCC3
GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H D
GPIO[6] ATADET0 AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
GPIO[7] SIO_OVT AC18 I/O Vcc3p3 N Y 3.3 Input pull high VCC3
GPIO[8] SIO_PME# E21 I/O VccSus3p3 N Y 3.3 Input SIO_PME# pull high VCC3_SB
GPIO[9] WLAN_PWRON E20 I/O VccSus3p3 N Y 3.3 Output pull high VCC3_SB SIGNAL DEVICE
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB (+BKL) MiniPCIeRST# MINI PCIE SLOT
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB (-BKL) LANRST# LAN 8111C
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB (+VOL) PCIRST_ICH7# BUFFER IC
GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB (-VOL) SCALER_RST# SCALER
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB H_CPURST# CPU
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC FWHRST# LPT Debug port
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GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A NC MCHRST# MCH
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input pull high VCC3
SMBCLK, SMBDATA DDR2, PCIEX1, CLKGEN, ICH7, ADT7464
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 NC
C
GPIO[21] SATA0GP
GPIO[22] PCIREQ[4]#
AF19 I/O
A13 I/O
Vcc3p3
Vcc3p3
N
N
N 3.3
N 3.3
Input
Input
pull high VCC3
PREQ#4
DDRII DIMM Config. C
DEVICE ADDRESS CLOCK
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input pull high VCC3
MCLK_A0/MCLK_A#0
GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change NC On Board A2H
MCLK_A1/MCLK_A#1
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 pull high VCC3 SB
MCLK_A0/MCLK_A#0
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 NC DIMM 1 A0H
MCLK_A1/MCLK_A#1
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 NC
GPIO[29] OC#2 C3 I/O VccSus3p3 N N 3.3 Input OC#5
GPIO[30] OC#2 A2 I/O VccSus3p3 N N 3.3 Input OC#6
GPIO[31] OC#2 B3 I/O VccSus3p3 N N 3.3 Input OC#7
GPIO[32] CLEAR_CMOS# AG18 I/O Vcc3p3 N N 3.3 1 CLEAR_CMOS#, ONLY pull high VCC3
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 NC
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
B GPIO[38] select SKU AD20 I/O Vcc3p3 N N 3.3 Input pull high VCC3 B
GPIO[39] select SKU AE20 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A GNT4#
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
GPI[15..0] can configured to cause a SMI# or SCI.
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
A A
MSI MICRO-STAR INt'L CO., LTD.
Title
GPIO MAP
Size Document Number Rev
1.0
MS-7438
Date: Friday, February 06, 2009 Sheet 5 of 36
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
CPU SIGNAL BLOCK
U10A
(9) H_A#[3..31] 0B changed 1
H_A#3 P21 V19 unstuff R712 refer
A[3]# ADS# H_ADS# (9)
H_A#4 H20 Y19
A[4]# BNR# H_BNR# (9) to CRB V0.8
0
ADDR GROUP
ADDR GROUP
H_A#5 N20 U21
A[5]# BPRI# H_BPRI# (9) U10B
H_A#6 R20 A[6]# (9) H_D#[0..63] H_D#[0..63] (9)
H_A#7 J19 T21 V_FSB_VTT H_D#0 Y11 R3 H_D#32
A[7]# DEFER# H_DEFER# (9) D[0]# D[32]#
H_A#8 N19 T19 H_D#1 W10 R2 H_D#33
A[8]# DRDY# H_DRDY# (9) D[1]# D[33]#
H_A#9 G20 Y18 H_D#2 Y12 P1 H_D#34
A[9]# DBSY# H_DBSY# (9) D[2]# D[34]#
CONTROL
H_A#10 M19 R712 H_D#3 AA14 N1 H_D#35
A[10]# D[3]# D[35]#
DATA GRP0
H_A#11 H21 T20 H_BR#0 (9) X_330R0402-1 H_D#4 AA11 M2 H_D#36
A[11]# BR0# D[4]# D[36]#
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DATA GRP2
H_A#12 L20 H_D#5 W12 P2 H_D#37
H_A#13 A[12]# H_IERR# H_D#6 D[5]# D[37]# H_D#38
M20 A[13]# IERR# F16 AA16 D[6]# D[38]# J3
H_A#14 K19 V16 R27 H_D#7 Y10 N3 H_D#39
A[14]# INIT# H_INIT# (19) D[7]# D[39]#
H_A#15 J20 1KR1%0402 H_D#8 Y9 G3 H_D#40
H_A#16 A[15]# H_D#9 D[8]# D[40]# H_D#41
L21 A[16]# LOCK# W20 H_LOCK# (9) Y13 D[9]# D[41]# H2
(9) H_ADSTB#0 K20 H_D#10 W15 N2 H_D#42
ADSTB[0]# H_DBI#[0..3] (9) D[10]# D[42]#
T1 D17 D15 H_D#11 AA13 L2 H_D#43
AP0 RESET# H_CPURST# (9) D[11]# D[43]#
H_REQ#0 N21 W18 H_RS#0 H_D#12 Y16 M3 H_D#44
H_REQ#1 REQ[0]# RS[0]# H_RS#1 H_D#13 D[12]# D[44]# H_D#45
(9) H_REQ#[0..4] J21 REQ[1]# RS[1]# Y17 W13 D[13]# D[45]# J2
H_REQ#2 G19 U20 H_RS#2 H_RS#[0..2] (9) H_D#14 AA9 H1 H_D#46
H_REQ#3 REQ[2]# RS[2]# H_D#15 D[14]# D[46]# H_D#47
P20 REQ[3]# TRDY# W19 H_TRDY# (9) W9 D[15]# D[47]# J1
C H_REQ#4 R19 Y14 K2 C
REQ[4]# (9) H_DSTBN#0 DSTBN[0]# DSTBN[2]# H_DSTBN#2 (9)
HIT# AA17 H_HIT# (9) (9) H_DSTBP#0 Y15 DSTBP[0]# DSTBP[2]# K3 H_DSTBP#2 (9)
H_DBI#0 H_DBI#2
(9) H_A#[3..31] HITM# V20 H_HITM# (9)0B changed 2 W16 DINV[0]# DINV[2]# L1
H_A#17 C19 RN35 T2 V9 M4 T3
H_A#18 A[17]# H_BPM#0 DP#0 DP#2
F19 A[18]# BPM[0]# K17 1 2 V_FSB_VTT (9) H_D#[0..63] H_D#[0..63] (9)
H_A#19 E21 J18 H_BPM#1 3 4 H_D#16 AA5 C2 H_D#48
H_A#20 A[19]# BPM[1]# H_BPM#2 H_D#17 D[16]# D[48]# H_D#49
A16 H15 5 6 Y8 G2
XDP/ITP SIGNALS
H_A#21 A[20]# BPM[2]# H_BPM#3 8P4R-51R0402 H_D#18 D[17]# D[49]# H_D#50
D19 A[21]# BPM[3]# J15 7 8 W3 D[18]# D[50]# F1
ADDR GROUP 1
H_A#22 C14 K18 H_BPM#4 H_D#19 U1 D3 H_D#51
H_A#23 A[22]# PRDY# PREQ# 0B Change 13 H_D#20 D[19]# D[51]# H_D#52
C18 A[23]# PREQ# J16 W7 D[20]# D[52]# B4
DATA GRP1
DATA GRP1
DATA GRP3
H_A#24 C20 M17 H_TCK 51R1%0402 H_D#21 W6 E1 H_D#53
H_A#25 A[24]# TCK H_TDI R713 V_FSB_VTT H_D#22 D[21]# D[53]# H_D#54
E20 A[25]# TDI N16 Y7 D[22]# D[54]# A5
H_A#26 D20 M16 X_51R1%0402 H_D#23 AA6 C3 H_D#55
H_A#27 A[26]# TDO H_TMS R727 H_IERR# R1 1KR1%0402 H_D#24 D[23]# D[55]# H_D#56
B18 A[27]# TMS L17 Y3 D[24]# D[56]# A6
H_A#28 C15 K16 H_TRST# H_D#25 W2 F2 H_D#57 0B changed 6
V_FSB_VTT H_A#29 A[28]# TRST# R715 X_150R1%0402-1 RN1 C2 H_D#26 D[25]# D[57]# H_D#58
B16 A[29]# BR1# V15 C1 V3 D[26]# D[58]# C6 Change R4,R8 to 24.9R
H_A#30 B17 R723 R235 H_TDI 1 2 H_D#27 U2 B6 H_D#59
RN2 H_A#31 A[30]# D[27]# D[59]# R6,R9 to 49.9R.
C16 A[31]# PROCHOT# G17 H_PROCHOT# 22R1%0402 62R H_TMS 3 4 C0.1U25Y C0.1U25Y H_D#28 T3 D[28]# D[60]# B3 H_D#60
7 8 A17 E4 PREQ# 5 6 H_D#29 AA8 C4 H_D#61
A[32]# THERMDA CPU_TMPA (33) D[29]# D[61]#
5 6 B14 E5 7 8 8P4R-51R0402 H_D#30 V2 C7 H_D#62
THERM
A[33]# THERMDC VTIN_GND (33) D[30]# D[62]#
3 4 B15 H_D#31 W4 D2 H_D#63
8P4R-1KR0402 A[34]# H_PROCHOT_N D[31]# D[63]#
1 2 A14 A[35]# (9) H_DSTBN#1 Y4 DSTBN[1]# DSTBN[3]# E2 H_DSTBN#3 (9)
B19 ADSTB[1]# (9) H_DSTBP#1 Y5 DSTBP[1]# DSTBP[3]# F3 H_DSTBP#3 (9)
H_DBI#1 H_DBI#3
(9) H_ADSTB#1
M18 H17
Y6
R4
DINV[1]# DINV[3]# C5
D4
0.5" max length
T4 AP1 THERMTRIP# TRMTRIP# (19) T5 DP#1 DP#3 T6
H_TCK R2 51R1%0402 25 MIL AWAY FROM HIGH
H_TRST# R3 51R1%0402 GTLREF A7 T1 H_COMP0 R4 24.9R1%0402
GTLREF COMP[0] SPEED SIGNAL
(19) H_A20M# U18
T16
A20M#
R5
R7
X_1KR0402
X_1KR0402
U5
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