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A B C D E
SYSTEM DC/DC
AG1 Block Diagram
TPS51120 41
Project code: 91.4A901.001 INPUTS OUTPUTS
PCB P/N : 55.4A903.XXX
5V_S5
REVISION : 05225-1 DCBATOUT
Mobile CPU
3V_S5
CLK GEN. (Hannstar, GCE)
4 G792 PCB STACKUP 4
ICS954305D Yonah 478 19
SYSTEM DC/DC
(IDT CV155) TOP MAX8743EE 42
3
Celeron M 4, 5 VCC INPUTS OUTPUTS
TVO
14 S 1D05V_S0
HOST BUS 400/533/667MHz DCBATOUT
LVDS 14"WSXGA+ 1D8V_S3
DDR2 533/667MHz LCD 13
S
TPS51100 44
533/667 MHz RGB CRT
GND
11,12 CRT 1D8V_S3 DDR_VREF
Calistoga 14 BUTTOM
DDR2 533/667MHz
APL5332KAC 44
533/667 MHz 6,7,8,9,10 3D3V_S5 2D5V_S0
11,12 PCMCIA I/F
3 PCMCIA APL5912-U 44 3
DMI I/F 100MHz
TI SLOT
Support 3D3V_S5 1D5V_S0
Line In PCI 7412 PWR SW
29 TSP2220A TypeII
27
Codec AZALIA 27 MAXIM CHARGER
CARDBUS MAX8725+Max1773 43
29 ALC883 PCI BUS 1394
28
CardReader 1394 INPUTS OUTPUTS
CONN 26 MS/MS Pro/xD/
MIC In 24,25 BT+
MMC/SD/SDIO
6 in 1 18V 4.0A
26 DCBATOUT
Line Out UP+5V
(SPDIF)
OP AMP
ICH7-M Mini-PCI 5V 100mA
TV Tuner 30
29
G1421B LAN CPU DC/DC
29 ISL6262
10/100 TXFM RJ45 39,40
23 23
2INT.SPKR BCM4401-E 22 INPUTS OUTPUTS 2
PCIEx1 Mini Card*2
29 802.11A/B/G 26 VCC_CORE
DCBATOUT
Giga LAN 22 0~1.3V
BCM5798 48A
MODEM SPI I/F SPI
RJ11 MDC Card Flash
21
15,16,17,18
LPC BUS
PCI Express
SATA
PATA
SIO KBC LPC
New card USB NS HD64F2111BVC DEBUG
30 CONN.
3 PORT
21 87392 32 31 34
21
PWR SW MINI USB FIR 32 Touch INT.
1 TPS223130 HDD 20 CDROM Blue-tooth Pad 33 KB 33
1
18
Wistron Corporation
21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Taipei Hsien 221, Taiwan, R.O.C.
Title
BLOCK DIAGRAM
Size Document Number Rev
A3
AG1 -1
Date: Monday, January 09, 2006 Sheet 1 of 45
A B C D E
ICH7M Integrated Pull-up 954305D 27Mhz/LCDCLK Spread Calistoga Strapping Signals and
and Pull-down Resistors ICH7-M EDS 17837 1.5V1
and Frequency Selection Table Configuration EDS 17050 0.71
page 7
SS3 SS2 SS1 SS0
Byte9 bit6 bit5 bit4 Spread Amount% page 3 Pin Name Strap Description Configuration
EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], bit 7 CFG[2:0] FSB Frequency Select
GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, 0 0 0 0 -0.50 Down 001 = FSB533
ICH7 internal 20K pull-ups 011 = FSB667
LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] 0 0 0 1 -1.00 Down others = Reserved
4 LDRQ[0], LDRQ[1]/GPIO[41], 0 0 1 0 -1.50 Down CFG[4:3] Reserved 4
PWRBTN#, TP[3] 0 0 1 1 -2.00 Down CFG5 DMI x2 Select 0 = DMI x2
1 = DMI x4 (Default)
0 1 0 0 -0.75 Down CFG6 Reserved
DD[7], DDREQ ICH7 internal 11.5K pull-downs
0 1 0 1 -1.25 Down CFG7 0 = Reserved
CPU Strap 1 =Mobile CPU(Default)
ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs 0 1 1 0 -1.75 Down
Reserved
ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, 0 1 1 1 -2.25 Down CFG8
EE_CS,SPI_ARB, SPI_CLK, SPKR, 1 0 0 0 +-0.25 Center 0 = Reverse Lanes,15->0,14->1 ect..
CFG9 PCI Express Graphics 1= Normal operation(Default):Lane
1 0 0 1 +-0.5 Center Lane Reversal Numbered in order
USB[7:0][P,N] ICH7 internal 15K pull-downs
1 0 1 0 +-0.75 Center
CFG[11:10] Reserved
SATALED# ICH7 internal 15K pull-up 1 0 1 1 +-1.0 Center
XOR/ALL Z test 00 = Reserved
1 1 0 0 +-0.25 Center CFG[13:12] straps 01 = XOR mode enabled
LAN_CLK ICH7 internal 100K pull-down 10 = All Z mode enabled
1 1 0 1 +-0.5 Center 11 = Normal Operation
(Default)
1 1 1 0 +-0.75 Center
CFG[15:14] Reserved Reserved
ICH7M IDE Integrated Series 1 1 1 1 +-1.0 Center
CFG16 FSB Dynamic ODT 0 = Dynamic ODT Disabled
3 Termination Resistors Global R-comp Disable
1 = Dynamic ODT Enabled (Default)
0 = All R-comp Disable 3
CFG17 (All R-comps) 1 = Normal Operation (Default)
DD[15:0], DIOW#, DIOR#, DREQ,
approximately 33 ohm
PCI Routing page 16
CFG18 VCC Select 0 = 1.05V (Default)
DDACK#, IORDY, DA[2:0], DCS1#, 1 = 1.5V
DCS3#, IDEIRQ
IDSEL INT -> PIRQ REQ/GNT CFG19 DMI Lane Reversal 0 = Normal operation (Default):lane
A->G, B->B, Numbered in order
1 =Reverse Lane,4->0,3->1 ect...
7412 22 C->F, D->G 0
A/C -> E 0 = Only SDVO or PCIE x1 is
ICH7M Functional Strap Definitions page 16
MiniPCI 21 B/D -> E 1 CFG20 SDVO/PCIE
Concurrent
operational (Default)
1 =SDVO and PCIE x1 are operating
simultaneously via the PEG port
Signal Usage/When Sampled Comment LAN 23 A -> H 2 SDVOCRTL SDVO Present 0 = No SDVO Card present
ACZ_SDOUT XOR Chain Entrance/ Allows entrance to XOR Chain testing when TP3 _DATA (Default)
PCIE Port Config bit1, pulled low.When TP3 not pulled low at rising edge 1= SDVO Card present
Rising Edge of PWROK of PWROK,sets bit1 of RPC.PC(Config Registers: 1410 25 A->G, B->B, 0 NOTE: All strap signals are sampled with respect to the leading
offset 224h) edge of the Calistoga GMCH PWORK in signal.
ACZ_SYNC PCIE bit0, Sets bit0 of RPC.PC(Config Registers:Offset 224h)
Rising Edge of PWROK.
EE_CS Reserved This signal should not be pull high. History
EE_DOUT Reserved This signal should not be pull low.
6/6 drawing SA
2 GNT2# Reserved This signal should not be pull low. 2
7/11 Rename for placement
Top-Block Sampled low:Top-Block Swap mode(inverts A16 for
GNT3# Swap Override. all cycles targeting FWH BIOS space).
Rising Edge of PWROK. Note: Software will not be able to clear the
Top-Swap bit until the system is rebooted
without GNT3# being pulled down.
GNT5#/ Boot BIOS Destination Controllable via Boot BIOS Destination bit
GPIO17#, Selection. (Config Registers:Offset 3410h:bit 11:10).
GNT4#/ Rising Edge of PWROK. GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC.
GPIO48
DPRSLPVR Reserved This signal should not be pull high.
GPIO25 Reserved.
Rising Edge of RSMRST#. This signal should not be pull low.
INTVRMEN Integrated VccSus1_05 Enables integrated VccSus1_05 VRM when
VRM Enable/Disable. sampled high
Always sampled.
LINKALERT# Reserved Requires an external pull-up resistor.
REQ[4:1]# XOR Chain Selection.
Rising Edge of PWROK. TBD, Chapter 8.
1 1
SATALED# Reserved This signal should not be pull low.
Wistron Corporation
SPKR No Reboot. If sampled high, the system is strapped to the 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,
Rising Edge of PWROK. "No Reboot" mode(ICH7 will disable the TCO Timer Taipei Hsien 221, Taiwan, R.O.C.
system reboot feature). The status is readable
Title
via the NO REBOOT bit.
Reference
TP3 XOR Chain Entrance. This signal should not be pull low unless using Size Document Number Rev
A3
Rising Edge of PWROK. XOR Chain testing. AG1 -1
Date: Monday, January 09, 2006 Sheet 2 of 45
A B C D E
3D3V_S0
3D3V_S0 3D3V_S0
-1
R123
1 R74 2 3D3V_CLKPLL_S0 1 2 3D3V_48MPWR_S0 3D3V_CLKGEN_S0 1 R122 2
0R0603-PAD 5D1R3F-GP 0R0603-PAD
1
1
1
1
1
1
1
1
1
C137
SC2D2U10V3ZY-1GP
C147 C96 C139 C136 C114 C131 C115 C130 C88 C91
2 SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SC4D7U10V5ZY-3GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
2
2
2
2
2
2
2
4 4
SRN33J-5-GP-U
3D3V_S0 D_REFSSCLK_1 RN30 4 1 D_REFSSCLK 7
D_REFSSCLK#_1 3 2 D_REFSSCLK# 7
U15
1
34 PCLK_FWH R661 2 1 22R2J-2-GP RN22 2 3 SRN33J-5-GP-U CLK_MCH_3GPLL 7
R457 1 4 CLK_MCH_3GPLL# 7
10KR2J-3-GP R449 1 2 33R2J-2-GP PCLKCLK0 56 17
31 PCLK_KBC PCI0 LVDS
-1 22 PCLK_LAN R448 1 2 33R2J-2-GP PCLKCLK1 3 18 RN27 2 3 SRN33J-5-GP-U CLK_PCIE_ICH 16
R456 2 PCI1 LVDS#
TIPCI 25 PCLK_PCM_TI 1 0R2J-2-GP 1 R699 2PCLKCLK2 4 1 4 CLK_PCIE_ICH# 16
2
R454 2 PCI2
No TIPCI35 PCLK_PCM_ENE 1 0R2J-2-GP 33R2J-2-GP 5 PCI3 SRC1 19 CLK_MCH_3GPLL_1
SS_SEL FIR 32 PCLK_SIO R453 2 1 22R2J-2-GP PCLKCLK3 20 CLK_MCH_3GPLL_1# RN24 2 3 SRN33J-5-GP-U CLK_PCIE_LAN 22
H/L: 100/96MHz 30 PCLK_MINI MINI R452 1 2 33R2J-2-GP SS_SEL 9
SRC1#
22 CLK_PCIE_ICH_1 1 GIGA 4 CLK_PCIE_LAN# 22
PCIF1/SEL100/96# SRC2
1
16 CLK_ICHPCI R459 1 2 33R2J-2-GP ITP_EN 8 23 CLK_PCIE_ICH_1#
R455 PCIF0/ITP_EN SRC2# CLK_PCIE_LAN_1 RN20
1 2 SRC3 24 2 3 SRN33J-5-GP-U CLK_PCIE_SATA 15
10KR2J-3-GP R460 10KR2J-3-GP 55 25 CLK_PCIE_LAN_1# 1 4
16 PM_STPPCI# PCI_STOP# SRC3# SATA CLK_PCIE_SATA# 15
DY H/L : CPU_ITP/SRC7 26 CLK_PCIE_SATA_1
SRC4 CLK_PCIE_SATA_1# RN21
27 1 4 SRN33J-5-GP-U CLK_PCIE_NEW 30
2
SRC4# CLK_PCIE_NEW_1
11,18 SMBC_ICH 46 SCL SRC5 31
CLK_PCIE_NEW_1#
2 NEW 3 CLK_PCIE_NEW# 30
11,18 SMBD_ICH 47 SDA SRC5# 30
33 CLK_PCIE_MINI1_1 RN23 1 4 SRN33J-5-GP-U CLK_PCIE_MINI1 26
SRC6 CLK_PCIE_MINI1_1#
SRC6# 32 2 3 CLK_PCIE_MINI1# 26
3
7 D_REFCLK 1 4 D_REFCLK_1 14 3
D_REFCLK#_1 DOT96
7 D_REFCLK# 2 3 15 DOT96# CPU2_ITP/SRC7 36 MINIC
SRN33J-5-GP-U RN34 35
C283 CPU2_ITP#/SRC7#
1 2 GEN_XTAL_IN 50 44 CLK_CPU_BCLK_1 RN33 3 2 SRN33J-5-GP-U CLK_CPU_BCLK 4
GEN_XTAL_OUT_R GEN_XTAL_OUT 49 XTAL_IN CPU0 CLK_CPU_BCLK_1#
1 2 XTAL_OUT CPU0# 43 4 1 CLK_CPU_BCLK# 4
1
SC20P50V2JN-1GP X3 R116 470R2J-2-GP 41
R439 1 CPU1
32 CLK14_SIO 2 22R2J-2-GP CPU1# 40 CLK_MCH_BCLK_1 RN37 3 2 SRN33J-5-GP-U CLK_MCH_BCLK 6
X-14D31818M-31GP 16 CLK_ICH14 R445 1 2 22R2J-2-GP GEN_REF 52 CLK_MCH_BCLK_1# 4 1 CLK_MCH_BCLK# 6
C278 82.30005.831 475R2F-L1-GP 2 R86 1GEN_IREF 39 REF
54 PM_STPCPU# 16
2
IREF CPU_STOP# CPU_SEL2
1 2 FSC/TEST_SEL 53 CPU_SEL2 4,7
16 CPU_SEL1 CPU_SEL1 4,7
SC20P50V2JN-1GP 3D3V_S0 FSB/TEST_MODE CPU_SEL0_1 22R2J-2-GP 1 R435
10 VTT_PWRGD#/PD USB48/FSA 12 2 CLK48_ICH 16
22R2J-2-GP 1 R437 2 CLK48_CARDBUS 25
R662
1 2 CPU_SEL0 4,7
1
2 34 3D3V_CLKGEN_S0 2K2R2J-2-GP
VSS_PCI VDD_SRC
6 VSS_PCI VDD_SRC 21
R101 DY
10KR2J-3-GP 51 7
VSS_REF VDD_PCI
45 1
2
VSS_CPU VDD_PCI
38 CLK_EN# 38 VSSA
13 VSS48 VDD_REF 48
29 VSS_SRC VDD_CPU 42
37 3D3V_CLKPLL_S0
VDDA 3D3V_48MPWR_S0
VDD48 11
VDD_SRC 28
IDTCV125PAG-GP 71.00125.A0W
2 2
EMI capacitor
PCLK_SIO 1 2 EC29 DY
RN31 SC10P50V3JN-GP
1D05V_S0 D_REFSSCLK# 1 4 CLK_ICH14 1 2 EC26 DY
D_REFSSCLK 2 3 SC10P50V3JN-GP
SRN49D9F-GP PCLK_MINI 1 2 EC28 DY
SC10P50V3JN-GP
1
1
1
CLK_PCIE_NEW 2 3
R447 R92 R438 RN83 CLK_PCIE_NEW# 1 NEW 4
DUMMY-R2 470R2J-2-GP CLK_PCIE_MINI1 SRN49D9F-GP
DUMMY-R2
2
DY CLK_PCIE_MINI1# 1 MINIC3
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