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Application Note 130
Cyrix III CPU Layout Guidelines for
133 MHz Bus Operation
Cyrix Processors
REVISION HISTORY
Date Version Revision
3/31/99 0.3 Page 4 Added paragraph under Introduction.
3/29/99 0.2 Removed notes 3 and 4 from Table 3.
Restored subscripts on page 7.
Minor typos corrected on page 27.
2/18/99 0.1 Initial Version C:\documentation\joshua\appnotes\cIII_layout.fm
Table of Contents
1.0 Introduction 4
2.0 Printed Circuit Board Stack-Up 5
3.0 GTL+ Bus Timing Analysis 7
4.0 Clock Layout Recommendations 13
5.0 GTL+ Layout Recommendations 17
6.0 Differences between Cyrix III and IntelTM CeleronTM Design Guides 27
Cyrix Application Note 130 - Cyrix III Layout Guideline for 133 MHz Operation 3
APPLICATION NOTE 130 Cyrix III Layout Guideline for
133 MHz Operation
1 Introduction
The Cyrix III processor is a next generation Cyrix processor. Cyrix III
employs a Socket 370 package, P6 bus protocol and operates with front
side bus speeds of 66 MHz, 100 MHz, and 133 MHz. The Cyrix III
processor system bus uses GTL+ signaling interface. The objective of this
layout guideline is to provide the system designer with the information
needed to achieve stable operation with 133 MHz front side bus. A Cyrix III
IBIS model is available if the system designer would like to verify his design,
but signal integrity analysis is not a requirement if the design falls within the
specifications of this guideline.
This document is to serve as a reference design to help new board
designers meet the 133 MHz specification. The Guidelines in this
document are for reference only, and are not a requirement for Cyrix
motherboard certification.
4 Cyrix Application Note 130 - Cyrix III Layout Guideline for 133 MHz Operation
2. Printed Circuit Board Stack-Up
Either a four-layer or six-layer stack-up can be used. In either case, it is important to control the
characteristic impedance to be 60 ohms within +/-10% for a 6 mil-wide trace. This characteristic
impedance improves signal integrity in many respects. Firstly, it improves signal integrity because it
is close to the value of the termination, 56 ohms. Secondly, it reduces overshoots and under-
shoots. Table 1 and Figure 1 describes a four-layer stack-up which would meets the characteristic
impedance requirement:
S TACK-U P P A RAMETER V ALUE
Height of Outer Dielectric 4.5 mil
Dielectric constant 4.5
Microstrip Base Cu Thickness 0.5 oz.
Microstrip Plating Cu Thickness 0.5 oz.
Power Plane Cu Thickness 1 oz.
Zo Typical 60 ohms
Table 1. Recommended Four Layer Stack-Up Parameters
1 oz. Cu
4.5 mil prepeg, r =4.5
Power Plane 1 oz. Cu
48 mil core,r=4.5
62 mils
Ground Plane 1 oz. Cu
4.5 mil prepeg, r =4.5
1 oz. Cu
Figure 1. Recommended Four Layer Stack-Up
Cyrix Application Note 130 - Cyrix III Layout Guideline for 133 MHz Operation 5
Table 2 and Figure 2 describe the recommended six layer stack-up which meets the characteristic
impedance requirements.
S TAC K-U P P ARAMETER V ALUE
Height of Outer Dielectric 4.5 mil
Dielectric constant for Microstrip Core 4.5
Dielectric constant for Stripline Traces 4.3
Microstrip Base Cu Thickness 0.5 oz
Microstrip Plating Cu Thickness 0.5 oz
Stripline Base Cu Thickness 0.5 oz.
Power Plane Cu Thickness 1 oz.
Zo Typical 60 ohms
Table 2. Recommended Four Layer Stack-Up Parameters
1 oz. Cu
4.5 mil dielectric, r =4.5
Power Plane 1 oz. Cu
6 mil prepeg,r =4.3
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