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E THE R LIN X P L U S
3 C 5 0 5
D EVE LOP E R I S G U IDE
Revision 3.0
3Com Corporation
May 2.1, 1986
PREFACE
This document is intended for use by sophisticated software
engineers who will either be writing application software that
will talk to the 3C505, or software that will actually reside on
the card. The user is expected to have a strong background in
microcomputer systems. It is recommended that the user browse
through the Intel 80186 Data Sheet and the Intel Lan Components
User's Manual before beginning (they are available through
Intel).
The manual is divided into the following chapters:
CH1~PTER 1 HARDWARE EXTERNAL REFERENCE SPECIFICATION (ERS)
Provides a description of the 3C505 architecture,
system resources and functional operation.
CHAPTER 2 HARDWARE INTERFACE SPECIFICATION
Describes the programmable registers used to
control, configure, and communicate with the
3C505.
CHAPTER 3 COMMAND INTERFACE SPECIFICATION
Describes the function and use of the command
level interface software supplied with the card.
APPENDIX A 80186 PERIPHERAL CONTROL BLOCK PROGRAMMING
Provides the values used in the 3C505 firmware to
configure the 80186 internal resources.
APPENDIX B 82586 CONFIGURATION
Provides the values used by the 3C505 firmware to
configure the 82586.
APPENDIX C 3CSOS DIAGNOSTIC
Describes the operation of the 3C505 diagnostic
utility program.
3D DEBUGGER
Describes a host program that uses a special debug
mode of the 3C505 to assist in debugging programs
running on the card.
APPENDIX E 3C50S DEVELOPER'S SOFTWARE DISKETTE
Describes the contents of the diskette that
accompanies the developer's kit.
APPENDIX F REVISION 2.0 ROM
Describes changes made in Revision 2.0 ROM code.
APPENDIX G REVISION 3.0 ROM
Describes changes made in Revision 3.0 ROM code.
TABLE OF CONTENTS
Page #
CHAPTER 1 - HARDWARE EXTERNAL REFERENCE SPECIFICATION
1.0 Introduction 1
1.1 Resources 1
1.2 Architecture 1
1.3 Address Maps 3
1.3.1 Adapter I/O map 3
1.3.2 Adapter memory map 3
1.3.3 Host I/O map 3
1.4 80186 Microprocessor 4
1.5 82586 Ethernet Coprocessor 4
1.6 Network Interface 5
1.6.1 82586 Serial Interface 5
1.6.2 8023 Manchester Converter 5
1.6.3 Transceiver 5
1.7 Adapter Firmware ROM 6
1.S Adapter RAM 6
1.9 Host-Adapter Interface 9
1.9.1 Command Register 9
1.9.2 Data Register 9
1~9.3 Data Register configuration 10
1.9.4 DMA Transfers 11
1.9.5 Status Flags 12
1.10 Adapter Interrupts 13
1.10.1 Internal Interrupts 13
1.10.2 External Interrupts 13
1.11 Host Interrupts 14
1.12 Resetting the Adapter 15
1.13 Ethernet Address 15
1.14 LED Indicators 15
1.15 Host ROM 16
CHAPTER 2 - HARDWARE INTERFACE SPECIFICATION
2.0 Introduction 17
2.1 Conunand Register 1S
2.2 Data Register 18
2.3 Host Control Register 19
2.4 Host status Register 21
2.5 Host Aux DMA Register 23
2.6 Adapter Control Register 23
2.7 Adapter status Register 25
CHAPTER 3 - COMMAND INTERFACE SPECIFICATION
3.0 Introduction 28
3.1 Primary Command Block structure 28
3.1.1 status Flag Usage for PCB Transfer 30
3.1.2 Host to Adapter Request 30
3.1.3 Adapter to Host Request or Response 31
3.2 PCB Commands 32
3.2.1 Host to 3C505 PCB Formats 32
3.2.2 3C505 to Host PCB Formats 37
3.3 System ROM Utilities 41
3.3.1 Host I/O support: INT SOH 41
3.3.2, Network I/O S~◦ Jabse Service Manual Search 2024 ◦ Jabse Pravopis ◦ onTap.bg ◦ Other service manual resources online : Fixya ◦ eServiceinfo